Round Robin Arbiter with parameters

A

Amir

Guest
Hi,
I want to implement a Round Robin Arbiter which has parameter inputs,
to determine what is the percentage grant for each client.
for example, let's say I have 2 clients , and the grant parameters are
30% 70%, so ,30% of the grants are for client 1 and 70% of the grants
are for client 2, is this implementable with Verilog? How would the
State Machine look like?

Thanks
-Amir
 
On Thu, 11 Sep 2008 23:48:50 -0700 (PDT), Amir <sting.t2@gmail.com>
wrote:

Hi,
I want to implement a Round Robin Arbiter which has parameter inputs,
to determine what is the percentage grant for each client.
for example, let's say I have 2 clients , and the grant parameters are
30% 70%, so ,30% of the grants are for client 1 and 70% of the grants
are for client 2, is this implementable with Verilog? How would the
State Machine look like?
Click to expand...
If it has arbitration weights, how can it be round-robin?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Fri, 12 Sep 2008 00:34:19 -0700 (PDT), Michael wrote:

If it has arbitration weights, how can it be round-robin?

Jonathan: Very easy - each master gets an access for specific time one
after other.
Click to expand...
Ah, thanks. I see what you mean. Not something I've
ever needed to deal with, whereas cyclic arbiters are
common (and quite useful).

Amir: I don't believe you need a state machine for that. Simple
counter will do the job.
Click to expand...
But presumably you need to skip the counts for any master
that is currently not requesting access?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Sep 12, 10:11 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Thu, 11 Sep 2008 23:48:50 -0700 (PDT), Amir <sting...@gmail.com
wrote:

Hi,
I want to implement a Round Robin Arbiter which has parameter inputs,
to determine what is the percentage grant for each client.
for example, let's say I have 2 clients , and the grant parameters are
30% 70%, so ,30% of the grants are for client 1 and 70% of the grants
are for client 2, is this implementable with Verilog? How would the
State Machine look like?

If it has arbitration weights, how can it be round-robin?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Jonathan: Very easy - each master gets an access for specific time one
after other.
Amir: I don't believe you need a state machine for that. Simple
counter will do the job.
 
On Sep 12, 11:30 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Fri, 12 Sep 2008 00:34:19 -0700 (PDT), Michael wrote:
If it has arbitration weights, how can it be round-robin?
Jonathan: Very easy - each master gets an access for specific time one
after other.

Ah, thanks. I see what you mean. Not something I've
ever needed to deal with, whereas cyclic arbiters are
common (and quite useful).

Amir: I don't believe you need a state machine for that. Simple
counter will do the job.

But presumably you need to skip the counts for any master
that is currently not requesting access?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
I meant counter for the cycles. You also need "current master"
register and "next master" function. That is it.
 
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