$rose in clocking block property

P

Prabhat

Guest
interface myinterface ( input clk, reset, cpreq_valid);

clocking monitor_cb @(posedge clk);
default input #1step output #0;
input reset;
input cpreq_valid;

property prop;
disable iff(reset)
$rose(cpreq_valid);
endproperty

endclocking : monitor_cb

cover_prop_A: cover property (monitor_cb.prop);

always @(posedge clk)
cover_prop_B: cover property ($rose(cpreq_valid));

endinterface

In above interface, *cover_prop_B* is matching but not *cover_prop_A*.
They both should match. Can someone explain why this is happening? I
am using vcs. Here is what SystemVerilog spec says about $rose:

A value change function detects the change in the sampled value of an
expression. The clocking event is
used to obtain the sampled value of the argument expression at a clock
tick prior to the current simulation
time unit. Here, the current simulation time unit refers to the
simulation time unit in which the function is
evaluated. This sampled value is compared against the value of the
expression determined at the prepone
time of the current simulation time unit. The result of a value change
expression is true or false and can be
used as a boolean expression.
 
On Thu, 25 Mar 2010 14:08:50 -0700 (PDT), Prabhat wrote:

In above interface, *cover_prop_B* is matching but not *cover_prop_A*.
They both should match. Can someone explain why this is happening?
The two properties are different: one has a reset, the other
doesn't. Is this relevant?

It is curious that you're using "disable iff (reset)" when
"reset" is the clocking-block sampled value. My guess is
that this represents a misunderstanding, but without a
description of your expected protocol I can't be sure.

Final, stupid question: have you got reset in the right
polarity?
--
Jonathan Bromley
 

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