P
Prabhat
Guest
interface myinterface ( input clk, reset, cpreq_valid);
clocking monitor_cb @(posedge clk);
default input #1step output #0;
input reset;
input cpreq_valid;
property prop;
disable iff(reset)
$rose(cpreq_valid);
endproperty
endclocking : monitor_cb
cover_prop_A: cover property (monitor_cb.prop);
always @(posedge clk)
cover_prop_B: cover property ($rose(cpreq_valid));
endinterface
In above interface, *cover_prop_B* is matching but not *cover_prop_A*.
They both should match. Can someone explain why this is happening? I
am using vcs. Here is what SystemVerilog spec says about $rose:
A value change function detects the change in the sampled value of an
expression. The clocking event is
used to obtain the sampled value of the argument expression at a clock
tick prior to the current simulation
time unit. Here, the current simulation time unit refers to the
simulation time unit in which the function is
evaluated. This sampled value is compared against the value of the
expression determined at the prepone
time of the current simulation time unit. The result of a value change
expression is true or false and can be
used as a boolean expression.
clocking monitor_cb @(posedge clk);
default input #1step output #0;
input reset;
input cpreq_valid;
property prop;
disable iff(reset)
$rose(cpreq_valid);
endproperty
endclocking : monitor_cb
cover_prop_A: cover property (monitor_cb.prop);
always @(posedge clk)
cover_prop_B: cover property ($rose(cpreq_valid));
endinterface
In above interface, *cover_prop_B* is matching but not *cover_prop_A*.
They both should match. Can someone explain why this is happening? I
am using vcs. Here is what SystemVerilog spec says about $rose:
A value change function detects the change in the sampled value of an
expression. The clocking event is
used to obtain the sampled value of the argument expression at a clock
tick prior to the current simulation
time unit. Here, the current simulation time unit refers to the
simulation time unit in which the function is
evaluated. This sampled value is compared against the value of the
expression determined at the prepone
time of the current simulation time unit. The result of a value change
expression is true or false and can be
used as a boolean expression.