rom initialisation question

[taco]

I try to convert the following vhdl into verilog:
architecture rtl of ROM is
signal A_r : std_logic_vector(11 downto 0);
type rom_type is array(0 to 2645) of std_logic_vector(7 downto 0);
signal ROM:rom_type := (
X"02",
X"00",
X"08",
X"12",

etc.
This vhdl code is synthesized super fast.(It's automatically generated code
from compiled c using some scripting).But what's the verilog equivalent of
this?
I tried something like:
always @(posedge Clk) begin
case (A)
12'h000 : D = 8'h02;
12'h001 : D = 8'h00;
12'h002 : D = 8'h08;
etc. but this results in a huge synthesize operation for the Xilinx ISE
program which I use. Anybody the syntax at hand for doing this?
Taco

 

[Dwayne Dilbeck]

The verilog equivalent is the following

reg [7:0] ROM [0:2654];

initial
$readmemh("datafile.txt",ROM);

where datafile has:

02
00
08
12
..
..
etc,


"taco" <tralalal@joepie.nl> wrote in message
news:fq69f6$tb5$1@usenet.uva.nl...

I try to convert the following vhdl into verilog:
architecture rtl of ROM is
signal A_r : std_logic_vector(11 downto 0);
type rom_type is array(0 to 2645) of std_logic_vector(7 downto 0);
signal ROM:rom_type := (
X"02",
X"00",
X"08",
X"12",

etc.
This vhdl code is synthesized super fast.(It's automatically generated
code
from compiled c using some scripting).But what's the verilog equivalent of
this?
I tried something like:
always @(posedge Clk) begin
case (A)
12'h000 : D = 8'h02;
12'h001 : D = 8'h00;
12'h002 : D = 8'h08;
etc. but this results in a huge synthesize operation for the Xilinx ISE
program which I use. Anybody the syntax at hand for doing this?
Taco

 

[John_H]

On Feb 28, 4:23 am, taco <trala...@joepie.nl> wrote:

I try to convert the following vhdl into verilog:
architecture rtl of ROM is
        signal A_r : std_logic_vector(11 downto 0);
        type rom_type is array(0 to  2645) of std_logic_vector(7 downto 0);
        signal ROM:rom_type := (
X"02",
X"00",
X"08",
X"12",

etc.
This vhdl code is synthesized super fast.(It's automatically generated code
from compiled c using some scripting).But what's the verilog equivalent of
this?
I tried something like:
always @(posedge Clk) begin
        case (A)
12'h000 : D = 8'h02;
12'h001 : D = 8'h00;
12'h002 : D = 8'h08;
etc. but this results in a huge synthesize operation for the Xilinx ISE
program which I use. Anybody the syntax at hand for doing this?
Taco

You can also target a specific BlockRAM primitive with INIT strings
rather than using the separate file. I prefer to keep everything in
the source file where reasonable, but some memories are better left
inferred and initialized with a $readmemh than instantiated as
BlockRAMs with INIT parameters.

- John_H