ROM in verilog

[Henry]

Dear All,
If I want to implent a ROM so that it can synthesized by Synopsys's
design analyzer, what kind of syntax should I used ? Is it the following
statement ok?

always@ (posedge clk or posedge rst or posedge read_data)
begin
if (rst == 1'b1)
begin
data <= 16'd0;
end
else
begin
if (read_data==1'b1)
case (address)
0 : data <= {8'd1, 8'd2 };
1 : data <= {8'd3, 8'd4 };
2 : data <= {8'd5, 8'd6 };
...
...
endcase
end
end

or should I initialize the ROM's content when I declare the ROM's
variable:"data"
which one is better?

Thank you very much.
Henry

 

[J o h n _ E a t o n (at)]

There are things you can synthesize and things that you can't.

You can synthesize flip_flops, latches and combinational logic.

You can't synthesize srams, roms, delay lines, plls and pads( sometimes).


If you know what your target silicon is then you find out how it wants
a rom design. It usually will require that you instantiate a module with
a particular name and supply the rom image in a specified file format.

If you don't know your target then create your own model and document it
so that whoever does put your design into silcon will know that they need
to create a rom.


The usual method is to grab a sram model and use a readmemh to load the
array at time 0.


John Eaton






Henry wrote:

Dear All,
If I want to implent a ROM so that it can synthesized by Synopsys's
design analyzer, what kind of syntax should I used ? Is it the following
statement ok?

always@ (posedge clk or posedge rst or posedge read_data)
begin
if (rst == 1'b1)
begin
data <= 16'd0;
end
else
begin
if (read_data==1'b1)
case (address)
0 : data <= {8'd1, 8'd2 };
1 : data <= {8'd3, 8'd4 };
2 : data <= {8'd5, 8'd6 };
...
...
endcase
end
end

or should I initialize the ROM's content when I declare the ROM's
variable:"data"
which one is better?

Thank you very much.
Henry

 

[Henry]

thx...

"J o h n _ E a t o n (at) hp . com (no spaces)" <"J o h n _ E a t o n (at)
hp . com (no spaces)"> ???????:44c8dce3$1@usenet01.boi.hp.com...

There are things you can synthesize and things that you can't.

You can synthesize flip_flops, latches and combinational logic.

You can't synthesize srams, roms, delay lines, plls and pads( sometimes).


If you know what your target silicon is then you find out how it wants
a rom design. It usually will require that you instantiate a module with
a particular name and supply the rom image in a specified file format.

If you don't know your target then create your own model and document it
so that whoever does put your design into silcon will know that they need
to create a rom.


The usual method is to grab a sram model and use a readmemh to load the
array at time 0.


John Eaton






Henry wrote:
Dear All,
If I want to implent a ROM so that it can synthesized by
Synopsys's design analyzer, what kind of syntax should I used ? Is it the
following statement ok?

always@ (posedge clk or posedge rst or posedge read_data)
begin
if (rst == 1'b1)
begin
data <= 16'd0;
end
else
begin
if (read_data==1'b1)
case (address)
0 : data <= {8'd1, 8'd2 };
1 : data <= {8'd3, 8'd4 };
2 : data <= {8'd5, 8'd6 };
...
...
endcase
end
end

or should I initialize the ROM's content when I declare the ROM's
variable:"data"
which one is better?

Thank you very much.
Henry