rocketio

N

news.verizon.net

Guest
Hi,
I would like some help from roketio users to find what is the maximum
realizable freq we can get out of it. I hear that although it supports upto
3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval board
which has charaterized the performance. Thanks much

Thomas
 
news.verizon.net wrote:
Hi,
I would like some help from roketio users to find what is the maximum
realizable freq we can get out of it. I hear that although it supports upto
3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval board
which has charaterized the performance. Thanks much

Thomas
Click to expand...
The RocketIO MGTs in the Virtex-II Pro family have a bandwidth up to
3.125 Gbps (not GHz) using the -6 and -7 speed grades and
flipchip (FF) packages. The slower -5 speed grade is rated for
2.000 Gbps and the wirebond (FG) packages are rated for 2.50 Gbps.

Our Virtex-II Pro X and Virtex-4 families have higher bandwidth
RocketIO MGTs and can operate above 10 Gbps.

You can purchase the board (HW-V2P-ML321) that is used for RocketIO
characterization through any Xilinx distributor or through our
online store at http://www.xilinx.com/ml321/ in addition to the
ML321 with a XC2VP7-FF672-6C device we also sell the HW-V2P-ML323
with a XC2VP50-FF1152-6C device and the HW-V2P-ML325 with a
XC2VP70-FF1704-6C device, both of which can also be found in our
online store.

Ed
 
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
Our Virtex-II Pro X and Virtex-4 families have higher bandwidth
RocketIO MGTs and can operate above 10 Gbps.
Click to expand...
Virtex 4 can do up to 11.1Gb/s to be exact.

--

Wing Wong.
 
"news.verizon.net" <res0rsef@verizon.net> schrieb im Newsbeitrag
news:DZK_d.4272$uw6.817@trnddc06...
Hi,
I would like some help from roketio users to find what is the maximum
realizable freq we can get out of it. I hear that although it supports
upto
3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval
board
Click to expand...

3.125 Gbit/s, not GHz. This is the line data rate. Effective data rate is
only 2.5 Gbits/s due to line encoding using 8B/10B encoder (encodes 8 data
bits into 10 data bits to guarantee a constant DC level and transition
density) Virtex4 supports also 64B/66B encoding (which is much more
effcient).

Regards
Falk
 
Falk,

You could decide to scramble the data and not use 8B10B, but then you
would have to be sure your scrambling never violated run length, or DC
imbalance issues, and you could live with scrambling multiplying a
single error into to more than one.

That way you could actually get 3.125 Gbs in V2 Pro, or 10 Gb/s in V2
Pro-X, or 10 Gbs in V4.

Austin

Falk Brunner wrote:

"news.verizon.net" <res0rsef@verizon.net> schrieb im Newsbeitrag
news:DZK_d.4272$uw6.817@trnddc06...

Hi,
I would like some help from roketio users to find what is the maximum
realizable freq we can get out of it. I hear that although it supports

upto

3.125Ghz, you can only get only upto 2.5Ghz. Also, can I get any eval

board

3.125 Gbit/s, not GHz. This is the line data rate. Effective data rate is
only 2.5 Gbits/s due to line encoding using 8B/10B encoder (encodes 8 data
bits into 10 data bits to guarantee a constant DC level and transition
density) Virtex4 supports also 64B/66B encoding (which is much more
effcient).

Regards
Falk
Click to expand...
 
"austin" <austin@xilinx.com> schrieb im Newsbeitrag
news:d1hqit$ka91@cliff.xsj.xilinx.com...
Falk,

You could decide to scramble the data and not use 8B10B, but then you
would have to be sure your scrambling never violated run length, or DC
imbalance issues, and you could live with scrambling multiplying a
single error into to more than one.
Click to expand...
Hmmm, since scrambling works reasonable well (all long distance traffic on
fiber optics is SONET/SDH) so it is a good option. But maybe a soft 64B/66B
encoder (V2P) let you sleep much more relaxed and so its worth the silicone.

Regards
Falk
 
Thanks for all the response. There is a very good app note(xapp681) from
xilinx by John Snow bypassing MGT 8B/10B used as HD Receiver. Source code
included.
Thomas


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3a3h36F67qf7aU1@individual.net...
"austin" <austin@xilinx.com> schrieb im Newsbeitrag
news:d1hqit$ka91@cliff.xsj.xilinx.com...
Falk,

You could decide to scramble the data and not use 8B10B, but then you
would have to be sure your scrambling never violated run length, or DC
imbalance issues, and you could live with scrambling multiplying a
single error into to more than one.

Hmmm, since scrambling works reasonable well (all long distance traffic on
fiber optics is SONET/SDH) so it is a good option. But maybe a soft
64B/66B
encoder (V2P) let you sleep much more relaxed and so its worth the
silicone.

Regards
Falk
Click to expand...
 
Falk,

I agree. Making your own link format, data protocol, etc. is a big
project. Best to use a standard.

Also, don't use silicone.

Austin
 
Are you sure about that 11 Gbps figure?

I've just had a look to the latest 'ug' from Xilinx
http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says it can
run up to 10.3125 Gbps... so... a pity that they are missing OTU2 (10.709
Gbps). This implies you still need an LIU between your optics and your V4 if
you want to go up to OTU2, doh! It will support OC192... probably with the
xpensive/fastest speed grade.

--
I.U. Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer Simpson

"Wing Fong Wong" <wing@stu.edu.au> wrote in message
news:d1gfc4$nap$1@enyo.uwa.edu.au...
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
Our Virtex-II Pro X and Virtex-4 families have higher bandwidth
RocketIO MGTs and can operate above 10 Gbps.


Virtex 4 can do up to 11.1Gb/s to be exact.

--

Wing Wong.
Click to expand...
 
I. Ulises Hernandez <delete@e-vhdl.com> wrote:
Are you sure about that 11 Gbps figure?
Click to expand...
11.1 was quoted at a xilinx conference I was attending last week.

--

Wing Wong.
 
I. Ulises Hernandez wrote:
Are you sure about that 11 Gbps figure?

I've just had a look to the latest 'ug' from Xilinx
http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says
it can
run up to 10.3125 Gbps... so... a pity that they are missing OTU2
(10.709
Gbps). This implies you still need an LIU between your optics and
your V4 if
you want to go up to OTU2, doh! It will support OC192... probably
with the
xpensive/fastest speed grade.
Click to expand...
http://www.google.com/search?&q=11.1+xilinx

shows lots of hits for 11.1 Gbps. In fact, it seems the only thing
saying 10.3125 Gbps is the most important document of them all, the ten
day old V4 RocketIO user guide.

BTW, I wouldn't be so quick to use this for OC-192 rate SONET
applications... you'll notice the below two pdf's go out of their way
to say that the V4 RocketIO is _OC-48_ compliant:

http://www.xilinx.com/publications/xcellonline/xcell_52/xc_pdf/xc_v4rocketio52.pdf
http://www.xilinx.com/company/press/kits/v4/v4_backgrounder.pdf

If it were OC-192 compliant, I suspect they'd be bragging about it.

Have fun,

Marc
 
"Wing Fong Wong" <wing@stud.com> wrote in message
news:d1nql7$r56$1@enyo.uwa.edu.au...
I. Ulises Hernandez <delete@e-vhdl.com> wrote:
Are you sure about that 11 Gbps figure?



11.1 was quoted at a xilinx conference I was attending last week.

--

Wing Wong.
Click to expand...
Hopefully any of the Xilinx guys in this group can enlighten us a little
bit...

Regards,

--
I.U. Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer Simpson ;O)
 
Marc,

Thanks for pointing me to the XCell paper, they seem to be claiming it's
OC-48 complaint... and it makes you doubt about OC-192 if they are not
shouting it from the roof tops... it could be jitter in the tx direction or
something.

As you said, there are lots of 11.1 Gbps figures but suddenly in their last
and most recent datasheet no more 11.1Gbps, only 10.3125 Gbps...

Regards,

--
I.U. Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer Simpson ;O)

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:1111460872.774966.176750@g14g2000cwa.googlegroups.com...
I. Ulises Hernandez wrote:
Are you sure about that 11 Gbps figure?

I've just had a look to the latest 'ug' from Xilinx
http://direct.xilinx.com/bvdocs/userguides/ug076.pdf and still says
it can
run up to 10.3125 Gbps... so... a pity that they are missing OTU2
(10.709
Gbps). This implies you still need an LIU between your optics and
your V4 if
you want to go up to OTU2, doh! It will support OC192... probably
with the
xpensive/fastest speed grade.

http://www.google.com/search?&q=11.1+xilinx

shows lots of hits for 11.1 Gbps. In fact, it seems the only thing
saying 10.3125 Gbps is the most important document of them all, the ten
day old V4 RocketIO user guide.

BTW, I wouldn't be so quick to use this for OC-192 rate SONET
applications... you'll notice the below two pdf's go out of their way
to say that the V4 RocketIO is _OC-48_ compliant:

http://www.xilinx.com/publications/xcellonline/xcell_52/xc_pdf/xc_v4rocketio52.pdf
http://www.xilinx.com/company/press/kits/v4/v4_backgrounder.pdf

If it were OC-192 compliant, I suspect they'd be bragging about it.

Have fun,

Marc
Click to expand...
 
I. Ulises Hernandez wrote:
Marc,

Thanks for pointing me to the XCell paper, they seem to be claiming it's
OC-48 complaint... and it makes you doubt about OC-192 if they are not
shouting it from the roof tops... it could be jitter in the tx direction or
something.

As you said, there are lots of 11.1 Gbps figures but suddenly in their last
and most recent datasheet no more 11.1Gbps, only 10.3125 Gbps...

Regards,
Click to expand...
Virtex-4 is not OC-192 compliant. The Sonet specifications have
extremely tight specifications that are very difficult to meet
with a universal transceiver. Virtex-4 is OC-48 compliant as we
have the necessary margins to meet the specs due to the design
needs for 10 Gbps.

Ed
 
Hello all,

I am working on a Virtex4 design and need to use RocketIO. Is there a
sample design based on Virtex4 RocketIO that I can leverage on. I
could not find any info in the Xilinx website other than the Virtex4
RocketIO user guide.

Thanks,
Ajith
 
My understanding is that the recovered clock from the RX side has too much jitter to be used for pretty much anything other than a transfer to a stable clock domain. i.e. I don't even think it can drive the FPGA fabric PLLs, let alone the transceiver PLL.

The usual way this is handled is to drive a PLL (not the internal FPGA PLLs, but an external discrete PLL) with a reference derived from the recovered clock. Then use the clock output of the PLL to drive the TX side of the transceiver. The PLL attenuates the jitter and you're good to go.

Disclosure: I know nothing about CPRI, but work with transceivers in an unrelated application.

Chris
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top