RocketIO transmission error

[Alex]

Hi,

i'm trying to use a RocketIO Infiniband connection on a Virtex2-Pro (XC2VP7
in a ML-300 board) to send
data from one transceiver to another. However the data is usually not
received correctly when sending it over
the cable (a 2.5 Gbps Infiniband cable), unless the cable is twisted in a
certain way. In serial loopback mode
the transmission works just fine.
Could the cable be broken or am I doing something wrong in the code?

Thanks
Alex


architecture arch of bert is
signal brefclk, usrclk, usrclk2, rst_gt, lock, configout, configout2,
rxcommadet, rxrealign, rxrecclk, txbuferr : std_logic;
signal txcharisk, rxchariscomma, rxcharisk, rxdisperr, rxnotintable,
rxrundisp, txkerr, txrundisp : std_logic_vector(0 downto 0);
signal rxbufstatus, rxlossofsync : std_logic_vector(1 downto 0);
signal rxclkcorcnt : std_logic_vector(2 downto 0);
signal rxdata_internal, txdata_internal, rxpattern, txpattern :
std_logic_vector(7 downto 0);
begin
rxdata <= rxdata_internal;
txdata <= txdata_internal;

transmit : process(usrclk)
variable count : integer := 0;
begin
if (rising_edge(usrclk)) then
if (count < 1000) then
txcharisk <= "1";
txdata_internal <= "00111100"; -- send comma
count := count + 1;
else
txcharisk <= "0";
txdata_internal <= "10101010"; -- send data

count := count + 1;
if (count = 2000) then
count := 0;
end if;
end if;
end if;
end process;

process(brefclk)
variable cnt : integer := 0;
begin
if (rising_edge(brefclk)) then
if (cnt >= 100) then
reset <= '0';
else
cnt := cnt + 1;
reset <= '1';
end if;
end if;
end process;

U_IBUFGDS: IBUFGDS_LVDS_25
port map (
I => clk_p,
IB => clk_n,
O => brefclk
);

Inst_infiniband_one_byte_tx : infiniband_one_byte_tx PORT MAP(
CONFIGENABLE => '0',
CONFIGIN => '0',
POWERDOWN => '0',
REFCLKSEL => '0',
BREFCLK => brefclk,
BREFCLK2 => '0',
RXUSRCLK => usrclk,
RXUSRCLK2 => usrclk2,
TXCHARDISPMODE => "0",
TXCHARDISPVAL => "0",
TXCHARISK => txcharisk,
TXDATA => txdata_internal,
TXINHIBIT => '0',
TXPOLARITY => '0',
TXRESET => rst_gt,
TXUSRCLK => usrclk,
TXUSRCLK2 => usrclk2,
CONFIGOUT => configout,
TXBUFERR => txbuferr,
TXKERR => txkerr,
TXN => txn,
TXP => txp,
TXRUNDISP => txrundisp
);

Inst_infiniband_one_byte_rx : infiniband_one_byte PORT MAP(
CONFIGENABLE => '0',
CONFIGIN => '0',
ENMCOMMAALIGN => '1',
ENPCOMMAALIGN => '1',
POWERDOWN => '0',
REFCLKSEL => '0',
BREFCLK => brefclk,
BREFCLK2 => '0',
RXN => rxn,
RXP => rxp,
RXPOLARITY => '0',
RXRESET => rst_gt,
RXUSRCLK => usrclk,
RXUSRCLK2 => usrclk2,
TXUSRCLK => usrclk,
TXUSRCLK2 => usrclk2,
CONFIGOUT => configout2,
RXBUFSTATUS => rxbufstatus,
RXCHARISCOMMA => rxchariscomma,
RXCHARISK => rxcharisk,
RXCLKCORCNT => rxclkcorcnt,
RXCOMMADET => rxcommadet,
RXDATA => rxdata_internal,
RXDISPERR => rxdisperr,
RXLOSSOFSYNC => rxlossofsync,
RXNOTINTABLE => rxnotintable,
RXREALIGN => rxrealign,
RXRECCLK => rxrecclk,
RXRUNDISP => rxrundisp
);

one_byte_clk_inst : one_byte_clk_fullrate
port map(
refclkin => brefclk,
rst => reset,
usrclk_m => usrclk,
usrclk2_m => usrclk2,
lock => lock
);

gt_reset_inst: gt_reset
port map(
usrclk2_m => usrclk2,
dcm_locked => lock,
rst => rst_gt
);
end architecture;