RocketIO in full bypass mode

[Antti Lukats]

Hallo,

I wonder if anyone has had any success using RocketIO in full 8b/10b bypass
mode in RX path ?

First a small BUG: The Arch wizard is faulty and the generated core will not
synthesize if simulation language is VHDL ( the generated VHDL can be
manually fixed, optionally if the simulation language is verilog then the
generate module does synthesis ok). This bug only appears when generating an
core with 1 byte datapath, 8/10b bypass and using VHDL as simulation lang.
In most other cases the Arch wizard is OK.

Well when the RocketIO receiver is in 8b/10b bypass and all smart features
disabled I would expect it to behave like simple deserializer - but it
doesnt seem to be so.

The receive data (with open input or even short circuit input) seems to be
either some random noise or 20 bit constant.

Any ideas what could cause this and if there is any cure against such
behaviour? Or maybe its normal functionality of MGTs ?

thanks in advance

Antti
PS if someone from Xilinx is not on vaccation I would appreciate an reply