A
Adarsh Kumar Jain
Guest
Hi All,
I am using a Xilinx V2Pro with 8 Rocket IOs all of which are being used.
My problem is that once in a while one or two channels misalign the data.
They mix up one byte of the Idle Word with one byte from Valid data
and then the whole subsequent data stream gets misaligned like that.
And sometimes i completely miss the first Valid Data Word.
Too me it looks like a timing problem, exactly what i can't figure out.
This is because, the problem is not fixed or repeatable. For example
sometimes
i see it happening on say just channel one, but if i power down the board
and restart,
then the problem either disappears or appears in another channel.
I have 8 xilinxs on the board and the problem is the same for all of them.
And within the Xilinx, all the channels are completely identical and so that
does not really "help" me in debugging.
Is there something i need to do to make the design more "robust" ?
Please advise,
Thanks in advance,
adarsh
I am using a Xilinx V2Pro with 8 Rocket IOs all of which are being used.
My problem is that once in a while one or two channels misalign the data.
They mix up one byte of the Idle Word with one byte from Valid data
and then the whole subsequent data stream gets misaligned like that.
And sometimes i completely miss the first Valid Data Word.
Too me it looks like a timing problem, exactly what i can't figure out.
This is because, the problem is not fixed or repeatable. For example
sometimes
i see it happening on say just channel one, but if i power down the board
and restart,
then the problem either disappears or appears in another channel.
I have 8 xilinxs on the board and the problem is the same for all of them.
And within the Xilinx, all the channels are completely identical and so that
does not really "help" me in debugging.
Is there something i need to do to make the design more "robust" ?
Please advise,
Thanks in advance,
adarsh