rocket IO MGT location constraint?

[Matthew E Rosenthal]

I am using a memec 2Vp20 board and I want to know which LOC constraint i
should use to be able to use rocket IO ports #6 and 7 or MGT # 19 and 21.
I have looked around and been unable to find any documents correlating
these port numbers or MGT numbers to actual LOC style constraint
any help would be appreciated

thanks

Matt

 

[Philip Freidin]

On Fri, 9 Apr 2004 21:59:49 -0400 (EDT), Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote:

I am using a memec 2Vp20 board and I want to know which LOC constraint i
should use to be able to use rocket IO ports #6 and 7 or MGT # 19 and 21.
I have looked around and been unable to find any documents correlating
these port numbers or MGT numbers to actual LOC style constraint
any help would be appreciated

thanks

Matt

The way I answer these type of questions is to run the FPGA editor,
on an empty design in the appropriate chip. This can also tell you
which CLBs are closest to which IOBs, the real order of IOBs (which
may not be obvious in BGA packages). And clock buffer placement,
which can be pretty important due to the arcane restrictions.

On the bottom edge of the die (looking at the die, which is the only
view that the editor gives), going left to right, the GT locations are

GT_X0Y0, between CLB slice column 15 and 16 (A BRAM column)
RXP=AP27, RNX=AP26, TXP=AP28, TXN=AP29
GT_X1Y0, between CLB slice column 39 and 40 (A BRAM column)
RXP=, RNX=, TXP=, TXN=
GT_X2Y0, between CLB slice column 51 and 52 (A BRAM column)
GT_X3Y0, between CLB slice column 75 and 76 (A BRAM column)

Along the top, from left to right

GT_X0Y1, between CLB slice column 15 and 16 (A BRAM column)
GT_X1Y1, between CLB slice column 39 and 40 (A BRAM column)
GT_X2Y1, between CLB slice column 51 and 52 (A BRAM column)
GT_X3Y1, between CLB slice column 75 and 76 (A BRAM column)


Pin numbers are for the FF1152 ball package

I assume that the Port/MGT numbers are something unique to the memec
board, so you will need to look at the schematics to finish resolving
this.

Philip Freidin


Philip Freidin
Fliptronics

 

[Philip Freidin]

On Fri, 9 Apr 2004 21:59:49 -0400 (EDT), Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote:

I am using a memec 2Vp20 board and I want to know which LOC constraint i
should use to be able to use rocket IO ports #6 and 7 or MGT # 19 and 21.
I have looked around and been unable to find any documents correlating
these port numbers or MGT numbers to actual LOC style constraint
any help would be appreciated

thanks

Matt

The way I answer these type of questions is to run the FPGA editor,
on an empty design in the appropriate chip. This can also tell you
which CLBs are closest to which IOBs, the real order of IOBs (which
may not be obvious in BGA packages). And clock buffer placement,
which can be pretty important due to the arcane restrictions.

On the bottom edge of the die (looking at the die, which is the only
view that the editor gives), going left to right, the GT locations are

GT_X0Y0, between CLB slice column 15 and 16 (A BRAM column)
RXP=AP27, RNX=AP26, TXP=AP28, TXN=AP29
GT_X1Y0, between CLB slice column 39 and 40 (A BRAM column)
RXP=AP19, RNX=AP18, TXP=AP20, TXN=AP21
GT_X2Y0, between CLB slice column 51 and 52 (A BRAM column)
RXP=AP15, RNX=AP14, TXP=AP16, TXN=AP17
GT_X3Y0, between CLB slice column 75 and 76 (A BRAM column)
RXP=AP7, RNX=AP6, TXP=AP8, TXN=AP9

Along the top, from left to right

GT_X0Y1, between CLB slice column 15 and 16 (A BRAM column)
RXP=A27, RNX=A26, TXP=A28, TXN=A29
GT_X1Y1, between CLB slice column 39 and 40 (A BRAM column)
RXP=A19, RNX=A18, TXP=A20, TXN=A21
GT_X2Y1, between CLB slice column 51 and 52 (A BRAM column)
RXP=A15, RNX=A14, TXP=A16, TXN=A17
GT_X3Y1, between CLB slice column 75 and 76 (A BRAM column)
RXP=A7, RNX=A6, TXP=A8, TXN=A9


Pin numbers are for the FF1152 ball package

I assume that the Port/MGT numbers are something unique to the memec
board, so you will need to look at the schematics to finish resolving
this.

Philip Freidin


Philip Freidin
Fliptronics