Rising edge of the clock

J

john

Guest
Hello,


The problem is that the "Q(0)" bit of the counter is not incrementing
at the rising edge of the "inc" signal instead its incrementing when
"inc" signal goes from high to low. I want to increment Q(0) at rising
edge of the "clk" and rising edge of the signal "inc".
Please Advice!!
Thanks
john


The code is given below:

C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);

Process ( State, input_signal )

Begin

Case State is


When E0 =>
Reset_A <='1';
inc <='0';
nextstate <=E1;


When E1 =>

Reset_A <='0';
inc <='1';

nextstate <=E2;

When E2 =>
Reset_A <='0';
inc <='0';

nextstate <=E1;


When others =>
nextstate <=E0;

End Case;

End Process;


-- ( 14 bit )


Entity counter is

Port (

Qout : out unsigned (13 downto 0);
CLK : in std_logic;
P : in std_logic;
count_equal: out std_logic;
Reset_c: in std_logic


);

End counter;

Architecture count_arch of counter is

Signal Q : unsigned (13 downto 0);

Begin

count_equal <= Q(0);


Process (Clk, Reset_c)

Begin


If (Reset_c = '1' ) then

Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0' );


Elsif ( Clk 'event and Clk='1' ) then

If (P= '1') then

Q <= Q + 1;

Qout <=Q;

End If;

End if;

End process;

End count_arch ;
 
conphiloso@hotmail.com (john) wrote in message news:<73aa8725.0411251246.19cb2de9@posting.google.com>...
Hello,


The problem is that the "Q(0)" bit of the counter is not incrementing
at the rising edge of the "inc" signal instead its incrementing when
"inc" signal goes from high to low. I want to increment Q(0) at rising
edge of the "clk" and rising edge of the signal "inc".
Please Advice!!
Thanks
john


The code is given below:

C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);

Process ( State, input_signal )

Begin

Case State is


When E0 =
Reset_A <='1';
inc <='0';
nextstate <=E1;


When E1 =

Reset_A <='0';
inc <='1';

nextstate <=E2;

When E2 =
Reset_A <='0';
inc <='0';

nextstate <=E1;


When others =
nextstate <=E0;

End Case;

End Process;


-- ( 14 bit )


Entity counter is

Port (

Qout : out unsigned (13 downto 0);
CLK : in std_logic;
P : in std_logic;
count_equal: out std_logic;
Reset_c: in std_logic


);

End counter;

Architecture count_arch of counter is

Signal Q : unsigned (13 downto 0);

Begin

count_equal <= Q(0);


Process (Clk, Reset_c)

Begin


If (Reset_c = '1' ) then

Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0' );


Elsif ( Clk 'event and Clk='1' ) then

If (P= '1') then

Q <= Q + 1;

Qout <=Q;

End If;

End if;

End process;

End count_arch ;
Click to expand...
John,
here you have single register pipeline which is introducing a clock
delay. you are reading incr which is generated w.r.t to clock in
another clocked process which is causing the delay. directly run you
counter in the states to avoid this delay.

-Neo
 
Hi Neo,

The state machine and the counter has the same clock. So, If two
processes have same clock then still they have delay between them.
Plus would u please explain that how am I using the single register
pipeline.
Please Advice!

Thanks
John
zingafriend@yahoo.com (Neo) wrote in message news:<e5de3dea.0411252100.60148c7b@posting.google.com>...
conphiloso@hotmail.com (john) wrote in message news:<73aa8725.0411251246.19cb2de9@posting.google.com>...
Hello,


The problem is that the "Q(0)" bit of the counter is not incrementing
at the rising edge of the "inc" signal instead its incrementing when
"inc" signal goes from high to low. I want to increment Q(0) at rising
edge of the "clk" and rising edge of the signal "inc".
Please Advice!!
Thanks
john


The code is given below:

C0: counter port map (Data_out_bus(13 downto 0),DPR_CLK,inc,eq_signal,Reset_A);

Process ( State, input_signal )

Begin

Case State is


When E0 =
Reset_A <='1';
inc <='0';
nextstate <=E1;


When E1 =

Reset_A <='0';
inc <='1';

nextstate <=E2;

When E2 =
Reset_A <='0';
inc <='0';

nextstate <=E1;


When others =
nextstate <=E0;

End Case;

End Process;


-- ( 14 bit )


Entity counter is

Port (

Qout : out unsigned (13 downto 0);
CLK : in std_logic;
P : in std_logic;
count_equal: out std_logic;
Reset_c: in std_logic


);

End counter;

Architecture count_arch of counter is

Signal Q : unsigned (13 downto 0);

Begin

count_equal <= Q(0);


Process (Clk, Reset_c)

Begin


If (Reset_c = '1' ) then

Q( 13 downto 0 ) <= ('0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0' );


Elsif ( Clk 'event and Clk='1' ) then

If (P= '1') then

Q <= Q + 1;

Qout <=Q;

End If;

End if;

End process;

End count_arch ;

John,
here you have single register pipeline which is introducing a clock
delay. you are reading incr which is generated w.r.t to clock in
another clocked process which is causing the delay. directly run you
counter in the states to avoid this delay.

-Neo
Click to expand...
 
john wrote:
Hi Neo,

The state machine and the counter has the same clock. So, If two
processes have same clock then still they have delay between them.
Plus would u please explain that how am I using the single register
pipeline.
Please Advice!

Thanks
John
zingafriend@yahoo.com (Neo) wrote in message news:<e5de3dea.0411252100.60148c7b@posting.google.com>...
conphiloso@hotmail.com (john) wrote in message news:<73aa8725.0411251246.19cb2de9@posting.google.com>...
Elsif ( Clk 'event and Clk='1' ) then
If (P= '1') then
Q <= Q + 1;
Qout <=Q;
End If;
Click to expand...
Here you have a register to clock in all the data bits, but the output
is delayed by another clock cycle to transfer it to the Qout register.
So the output changes two enabled clocks after the data is input. What
exactly are you trying to do?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
john wrote:

The problem is that the "Q(0)" bit of the counter is not incrementing
at the rising edge of the "inc" signal instead its incrementing when
"inc" signal goes from high to low. I want to increment Q(0) at rising
edge of the "clk" and rising edge of the signal "inc".
Please Advice!!
Click to expand...
Ok, here's a few examples:

1. Assumption: inc is generated on the same clock as the counter process:

PROCESS
BEGIN
WAIT UNTIL clk = '1';
inc_d <= inc;
IF inc = '1' AND inc_d = '0' THEN
Q <= Q + 1;
END IF;
Qout <= Q;
IF reset = '1' THEN
Q <= (OTHERS => '0');
Q_out <= (OTHERS => '0');
inc_d <= '0';
END IF;
END PROCESS;

2. Assumption: inc is generated on another clock as the counter process:

PROCESS
BEGIN
WAIT UNTIL clk = '1';
inc_c2c <= inc;
inc_meta <= inc_c2c;
inc_d <= inc_meta;
IF inc_meta = '1' AND inc_d = '0' THEN
Q <= Q + 1;
END IF;
Qout <= Q;
IF reset = '1' THEN
Q <= (OTHERS => '0');
Qout <= (OTHERS => '0');
inc_c2c <= '0';
inc_meta <= '0';
inc_d <= '0';
END IF;
END PROCESS;

Regards,

Pieter Hulshoff
 
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