A
ALuPin
Guest
Hi,
I have a question concerning my multi-clock design.
A PLL is fed with a 30MHz external clock.
There are three different clocks generated by the PLL:
c0 : 48MHz (for internal use)
c1 : 90MHz (for internal use)
e0 : 90MHz (for external use)
Apart from that I have a clock divider which generates an
12MHz clock out of c0 and an inverted 90MHz clock out of c1.
When I compile the whole design I get the following warnings:
1.Found 1 node(s) in clock paths which may be acting as ripple and/or
gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock CLOCK_DIVIDER
Do I have to make some assignment for that? How?
I would appreciate your help.
Rgds
André
I have a question concerning my multi-clock design.
A PLL is fed with a 30MHz external clock.
There are three different clocks generated by the PLL:
c0 : 48MHz (for internal use)
c1 : 90MHz (for internal use)
e0 : 90MHz (for external use)
Apart from that I have a clock divider which generates an
12MHz clock out of c0 and an inverted 90MHz clock out of c1.
When I compile the whole design I get the following warnings:
1.Found 1 node(s) in clock paths which may be acting as ripple and/or
gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock CLOCK_DIVIDER
Do I have to make some assignment for that? How?
I would appreciate your help.
Rgds
André