Ripple Clock for a counter

Hi All,

I want to count two different values. Since I need only one of them at
a time, I decided to use a single counter to count both of them (to
save hardware resources on FPGA). The two values require two different
clocks for counting (and even two different enables).

So I put a mux to select the enable and clock signal for my counter.

However, my synthesis tool (Quartus II) gave an error saying
"Encountered Ripple Clocks". I don't see a problem as such in muxing
the clocks in this case, because at a time only one of them is used in
the counter (The clocks are not derived from each other and are two
different sources).

Plz. suggest possible source of error in this case and if possible,
solution.

 

[sunny]

I don't see a problem as such in muxing
the clocks in this case, because at a time only one of them is used in
the counter
Hmm...even I don't see a problem. Infact, if your multiplexing logic

doesn't change after initial configuration, then it won't be a problem
to use the counter in this manner. However, you should take care that
your registers are reset when the switching happens and this transition
has no other negative consequences.

Plz. suggest possible source of error in this case and if possible,
solution.
Read "Multiplexed Clocks" section in "Design Considerations" in Quartus

II Handbook.

 

[Eric]

I'm not totally sure what your error is, but I'm guessing (without
seeing your code) that it might be the fact that you could possibly
have two independent processes asserting the same counter register.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity junk is
Port ( sys_clk : in std_logic;
CLK1 : in std_logic;
CLK2 : in std_logic;
CLK_SELECT : in std_logic;
Counter_out : out STD_LOGIC_VECTOR (7 downto 0));
end junk;

architecture Behavioral of junk is
signal Counter : STD_LOGIC_VECTOR (7 downto 0);
signal past_CLK1 : std_logic;
signal past_CLK2 : std_logic;
begin
Process (sys_clk)
Begin
if rising_edge(sys_clk) then --sys_clk runs faster than CLK1 & CLK2
Case CLK_SELECT is
When '0' =>
--rising edge of CLK1
If CLK1 = '1' and past_CLK1 = '0' then
Counter <= Counter + 1;
End if;
When '1' =>
--rising edge of CLK2
If CLK2 = '1' and past_CLK2 = '0' then
Counter <= Counter + 1;
End if;
When others =>
End case;
past_CLK1 <= CLK1;
past_CLK2 <= CLK2;
counter_out <= counter;
end if;
End process;


end Behavioral;

This code is untested but might make a good starting point.
Eric

 

[Eric]

If your trying to reduce the size of the logic, you can remove the
8-bit output latch by changing the VHDL a little.

End case;
past_CLK1 <= CLK1;
past_CLK2 <= CLK2;
end if;
End process;

counter_out <= counter;

end Behavioral;

Eric

 

Thanks Eric for the reply.

it might be the fact that you could possibly
have two independent processes asserting the same counter register.
No. In my case. I have a single process. The reset, count_enable and

clock, all three are multiplexed i.e. in one case, I have a different
set of reset, count_enable and clock and in another case, a different
set.

begin
Process (sys_clk)
But then you end up with three clocks. I don't have any system clock as

such at which I should start counting. Here you probably assume that
the transition of clk1 and clk2 will happen at sys_clk transtion.
However it is possible that CLK1 and CLK2 are faster than sys_clk and
have made transitions between two rising edges of sys_clk. Also, they
may not be harmonics of sys_clk.

 

Thanx Sunny.

Hmm...even I don't see a problem. Infact, if your multiplexing logic
doesn't change after initial configuration, then it won't be a problem
to use the counter in this manner. However, you should take care that
your registers are reset when the switching happens and this transition
has no other negative consequences.
If I follow these guidelines, then also get a warning. Probably it is

safe to ignore it, if one takes care of above points. Or not?

 

Maybe you have to set fmax constraints for the used clocks...

Rgds
André

 

[jens]

You're always asking for trouble when using more than one clock- if
that's necessary, make sure you double- and triple-check all signals
that cross clock domains. (Here's a good reference, even if some of
the advice may be a little extreme:
http://www.bawankule.com/verilogcenter/files/10_2.pdf)

Assuming that one of your clocks is suitable for both count values, I'd
use one clock and mux the preload values (or decode values, depending
on the target architecture).

Assuming static count values, use an LFSR
(http://en.wikipedia.org/wiki/LFSR) to minimize gate count.

That will generate a small & fast counter and also keep your compiler
happy.