ring oscillator

dear all,

these question is not regarding cadence rather its vlsi domain related
,since i can't find any group to discuss i am putting it here.

for a particular process technology there is a term called ring
oscillator inverter delay. this i got from the mosis web page.

my query is what is the physical meaning of this parameter ?

whether the delay value is fixed by the spice parameter values of the
transistors of the particular process ?

is there any group like this to discuss in the vlsi domain please
suggest me

with regards
selvakumar

 

[Hristo Brachkov]

Basically the idea is that you have a ring oscillator that consists of
several inverters (odd number). The frequency of osculation depends on the
delay of each inverter (the period of the oscillator should be the sum of
the delays - i.e. 3 inverters => T = 3*DELAY_TIME). Of course the delay of
the inverter depends on the transistor Ft.

Back to the question - the delay time of the inverter is the delay
introduced by the inverter - suppose you put signal at the inverter input,
the delay time is the time it takes that the signal appears at the output.


OK?



<selvakumar_in@hotmail.com> wrote in message
news:63f7196c.0310200419.55419c9c@posting.google.com...

dear all,

these question is not regarding cadence rather its vlsi domain related
,since i can't find any group to discuss i am putting it here.

for a particular process technology there is a term called ring
oscillator inverter delay. this i got from the mosis web page.

my query is what is the physical meaning of this parameter ?

whether the delay value is fixed by the spice parameter values of the
transistors of the particular process ?

is there any group like this to discuss in the vlsi domain please
suggest me

with regards
selvakumar

 

[John Gianni]

Basically the idea is that you have a ring oscillator that consists of
several inverters (odd number). The frequency of osculation depends on the
delay of each inverter (the period of the oscillator should be the sum of
the delays - i.e. 3 inverters => T = 3*DELAY_TIME). Of course the delay of
the inverter depends on the transistor Ft.

In addition, I'm told folks generally test with a fanout of n at each
interesting node m, e.g., a fanout of 1, 2, or 3 (for example) at node
17 (for example); and then they plot the curves & measure the delay.








"Hristo Brachkov" <hristob@SPAM.REMOVEcs.tut.fi> wrote in message news:<bn98m8$6vt$1@news.cc.tut.fi>...

Basically the idea is that you have a ring oscillator that consists of
several inverters (odd number). The frequency of osculation depends on the
delay of each inverter (the period of the oscillator should be the sum of
the delays - i.e. 3 inverters => T = 3*DELAY_TIME). Of course the delay of
the inverter depends on the transistor Ft.

Back to the question - the delay time of the inverter is the delay
introduced by the inverter - suppose you put signal at the inverter input,
the delay time is the time it takes that the signal appears at the output.


OK?



selvakumar_in@hotmail.com> wrote in message
news:63f7196c.0310200419.55419c9c@posting.google.com...
dear all,

these question is not regarding cadence rather its vlsi domain related
,since i can't find any group to discuss i am putting it here.

for a particular process technology there is a term called ring
oscillator inverter delay. this i got from the mosis web page.

my query is what is the physical meaning of this parameter ?

whether the delay value is fixed by the spice parameter values of the
transistors of the particular process ?

is there any group like this to discuss in the vlsi domain please
suggest me

with regards
selvakumar