retiming with Synplify Pro

[jgraham]

I am having problems gtting the retiming feature in Synplify to work.
I am coding in a style that utilizes the behavioural retiming(BRT) of
synopsys.
I code a mac as simple ((a*b) + c) + bulk delay. Synopsys then retimes
the code by pipelining the mac.

When I try to test this code in an fpga, Synplify does not retime the
registers properly.
Has anyone else tried this?

thanks
John

 

[Alan Nishioka]

john_p_graham@hotmail.com (jgraham) wrote in message news:<ea24bbb8.0308050632.2907332@posting.google.com>...

I am having problems gtting the retiming feature in Synplify to work.
I am coding in a style that utilizes the behavioural retiming(BRT) of
synopsys.
I code a mac as simple ((a*b) + c) + bulk delay. Synopsys then retimes
the code by pipelining the mac.

When I try to test this code in an fpga, Synplify does not retime the
registers properly.
Has anyone else tried this?

Yes, I tried it when Synplify first introduced retiming.
It had some effect, but no, it didn't work as I wanted it to,
so I didn't buy Synplify Pro.

However, I am still a happy user of Synplify Amateur.

Alan Nishioka
alann@accom.com