resolving instance bindings in AMS

[Sunil_rpine]

Hi,

I am running a mixed signals design and am having a problem in
simulating using the AMS simulator. The problem is with the
elaborations. The error I am getting has something to do with
resolving the instance bindings in the digital blocks.

Going into the details, my design has 3 digital modules, in which
various other sub-modules are being instantiated. While elaborating,
the sub-modules are not being resolved. An example of the error
message is below:

ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
ncelab: *E,CUCFUN: instance 'u1clock_mux' of the unit 'clock_mux' is
unresolved in 'SPARK_PLL.binary_top:verilog'.
ncelab: *E,CUCFUN: instance 'u2clock_mux' of the unit 'clock_mux' is
unresolved in 'SPARK_PLL.binary_top:verilog'.

clock_mux is a module instantiated in binary_top.

How do I avoid this error? My configuration table looks ok. All the
instance bindings are being listed with the exact name.

Thank you,
Sunil

 

[Riad KACED]

Hi Sunil,

There could be many reasons for this to happen.
It would have been very helpful if you have mentioned whether you are
running AMS designer in ADE or HED mode.
Anyway, there is a little document in your IC stream called: "AMS in
ADE Frequently Asked Questions" - $CDSHOME/doc/AMSinADEFAQ/
AMSinADEFAQ.pdf.
There is a section called 'Your design does not elaborate'; it does
outline the possible reasons and solutions behind elaboration
problems.
Could you give it a look and cross-check your design against what is
recommended in that doc ?

If you think you have included all the needed files, then I would
advice to clear out your working dir (remove all the .pak files) and
then re-run your compile/elaboration on 'all' the design, i.e not
incremental.

Hope this helps. If not, It might be helpful to mention your AMS
simulation more - ADE/HED, and your tool versions, IC/IUS.

Regards,
Riad.

 

[Sunil_rpine]

Hi Riad,

I found the document. It indeed helped me out this.
Thank you for your reply.

Thank you,
Sunil