Resolved Signals

[Dominik Fröhlich]

Hi there,

is anybody aware of a way to model a wired-or signal resolution function
which can be synthesized with XST? As far as I know XST does not
support user-defined resolution functions, however I need a wired-or
functionality in my design.

Regards

Dominik

 

[Tim Hubberstey]

Dominik Fröhlich wrote:

Hi there,

is anybody aware of a way to model a wired-or signal resolution function
which can be synthesized with XST? As far as I know XST does not
support user-defined resolution functions, however I need a wired-or
functionality in my design.

First, it is irrelevant whether or not your synthesizer supports
something if the target technology doesn't support it. As far as I know,
no Xilinx part supports wire-or as an internal function. However, I
don't use this kind of logic internal to a chip so I've never researched
it thoroughly.

You can get the equivalent of wire-or on external pins by using tristate
drivers with a pull-down resistor on one of the pins and only enabling
the driver when driving a '1';

wire_or_out_pin <= '1' when wire_or_out = '1' else 'Z';
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com