resol

[John Smith]

Hi,

What is the result of "s" after running this design? Im expecting "000000X0".

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch of test is
signal s: std_logic_vector(7 downto 0);
begin
s <= "0000001Z";
s <= "ZZZZZZ00";
end arch;


Thanks

 

[KJ]

"John Smith" <john.smith@hotmail.com> wrote in message
news:58c78$47003314$566534d5$28269@news.chello.hu...

Hi,

What is the result of "s" after running this design? Im expecting
"000000X0".

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch of test is
signal s: std_logic_vector(7 downto 0);
begin
s <= "0000001Z";
s <= "ZZZZZZ00";
end arch;

Simulation runs are going to take forever if you spend it querying a
newsgroup....Here are a couple of links that will help you to speed up
getting your results

http://en.wikipedia.org/wiki/GHDL
http://ghdl.free.fr/
http://www.google.com/search?hl=en&q=ghdl

For some general VHDL understanding...
http://esd.cs.ucr.edu/labs/tutorial/
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
http://www.google.com/search?hl=en&q=vhdl


Good luck

KJ

 

[John Smith]

KJ wrote:

"John Smith" <john.smith@hotmail.com> wrote in message
news:58c78$47003314$566534d5$28269@news.chello.hu...
Hi,

What is the result of "s" after running this design? Im expecting
"000000X0".

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch of test is
signal s: std_logic_vector(7 downto 0);
begin
s <= "0000001Z";
s <= "ZZZZZZ00";
end arch;


Simulation runs are going to take forever if you spend it querying a
newsgroup....Here are a couple of links that will help you to speed up
getting your results

http://en.wikipedia.org/wiki/GHDL
http://ghdl.free.fr/
http://www.google.com/search?hl=en&q=ghdl

For some general VHDL understanding...
http://esd.cs.ucr.edu/labs/tutorial/
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
http://www.google.com/search?hl=en&q=vhdl


Good luck

KJ

I ran it in a simulator but it responds "UUUUUUUU" not as I expected.

 

[KJ]

"John Smith" <john.smith@hotmail.com> wrote in message
news:9edd0$47003cb3$566534d5$29016@news.chello.hu...

KJ wrote:
"John Smith" <john.smith@hotmail.com> wrote in message
news:58c78$47003314$566534d5$28269@news.chello.hu...
Hi,

What is the result of "s" after running this design? Im expecting
"000000X0".

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch of test is
signal s: std_logic_vector(7 downto 0);
begin
s <= "0000001Z";
s <= "ZZZZZZ00";
end arch;


Simulation runs are going to take forever if you spend it querying a
newsgroup....Here are a couple of links that will help you to speed up
getting your results

http://en.wikipedia.org/wiki/GHDL
http://ghdl.free.fr/
http://www.google.com/search?hl=en&q=ghdl

For some general VHDL understanding...
http://esd.cs.ucr.edu/labs/tutorial/
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
http://www.google.com/search?hl=en&q=vhdl


Good luck

KJ



I ran it in a simulator but it responds "UUUUUUUU" not as I expected.

The "UUUUUUUU" is what you get at t=0 before you run the simulation,
"000000X0" is what you'll get at t=0 after you run the simulation (i.e.
run -all, or whatever is appropriate for your simulator). If you're not
getting that, then your simulator has issues.

KJ