P
Paul Marciano
Guest
Hi.
In my FPGA design I prefer a synchronous reset for everything.
This means my sequential blocks look like:
always @(posedge clk)
if (reset)
reset_stuff
else
real_stuff;
I notice that a lot of people use asynchronous resets:
always @(posedge clk or negedge reset)
if (!reset)
async_reset_stuff;
else
synchronous_stuff (possibly including a sync reset clause)
I think resets are a large topic, but is there anything obviously bad
in not using async resets?
Thanks,
Paul.
In my FPGA design I prefer a synchronous reset for everything.
This means my sequential blocks look like:
always @(posedge clk)
if (reset)
reset_stuff
else
real_stuff;
I notice that a lot of people use asynchronous resets:
always @(posedge clk or negedge reset)
if (!reset)
async_reset_stuff;
else
synchronous_stuff (possibly including a sync reset clause)
I think resets are a large topic, but is there anything obviously bad
in not using async resets?
Thanks,
Paul.