Reset style.

P

Paul Marciano

Guest
Hi.

In my FPGA design I prefer a synchronous reset for everything.

This means my sequential blocks look like:

always @(posedge clk)
if (reset)
reset_stuff
else
real_stuff;


I notice that a lot of people use asynchronous resets:

always @(posedge clk or negedge reset)
if (!reset)
async_reset_stuff;
else
synchronous_stuff (possibly including a sync reset clause)


I think resets are a large topic, but is there anything obviously bad
in not using async resets?

Thanks,
Paul.
 
Real world:
An ASIC of ours with a PCI interface was hooked up to a bridge that
doesn't provide a PCI clock during PCI reset. If the ASIC had an
asynchronous reset, this interface would have worked. How were we to know
the bridge would come out with screwy clocks?


"Paul Marciano" <pm940@yahoo.com> wrote in message
news:1131563369.664298.190150@g49g2000cwa.googlegroups.com...
Hi.

In my FPGA design I prefer a synchronous reset for everything.

This means my sequential blocks look like:

always @(posedge clk)
if (reset)
reset_stuff
else
real_stuff;


I notice that a lot of people use asynchronous resets:

always @(posedge clk or negedge reset)
if (!reset)
async_reset_stuff;
else
synchronous_stuff (possibly including a sync reset clause)


I think resets are a large topic, but is there anything obviously bad
in not using async resets?

Thanks,
Paul.
 
You may want to review a paper that I, Don Mills and Steve Golson gave
at Boston SNUG 2003 (a follow-on to the paper that Don and I did at San
Jose SNUG 2002) discussing many important considerations related to
synchronous and asynchronous reset design.

Look for the Boston SNUG 2003 paper:
"Asynchronous & Synchronous Reset - Design Techniques - Part Deux"

At the web page: www.sunburst-design.com/papers

Reset design is a topic that is poorly covered at the undergraduate
level and we teach an entire section on this topic in our Advanced
Verilog training.

Regards - Cliff Cummings
Verilog & SystemVerilog Guru
www.sunburst-design.com
 
Yes, I have high regards for Mr Cliff Cummings. And making reset
decisions is not a child's play :)

- svtechie
 

Welcome to EDABoard.com

Sponsor

Back
Top