Reset generation

[SKeffect]

Hi All,

I am working on a large design, consisting of say N modules and one
controller module.
The problem is that of generating reset for each module separately.
Now, there will be a master reset coming from pin which has to be
applied to all the modules.
Depending upon some conditions, the controller can reset one of the
modules. When i am working without this condition controlled reset, the
design is running at high speed but after inserting controller generated
reset, it sucks.

What i did, is to combine the master reset and the controlled reset and
generated a new reset signal. Then inserted a buffer, the output of
which will go to the modules. Not good enough.

Any brilliant ideas.

Regards,
Sunil

 

[sudhi]

Do you mean speed as in simulation speed? or max frequency after
synthesis?
If you are talking about max freq.
How big is your controlled reset generation logic? Depending on this
your new critical path can be the reset network. That could be one
reason behind the degradation of speed.
One solution is to ignore the reset network in your timing contraints.
This could be done with certain synthesis directives.

Hope this helps
Sudhi

 

[SKeffect]

sudhi wrote:

Do you mean speed as in simulation speed? or max frequency after
synthesis?

The struggle here is with synthesis.

If you are talking about max freq.
How big is your controlled reset generation logic? Depending on this

not that big, actually an AND of two registered internal signals.
after that i am putting a buf component and then driving the reset of
modules.

your new critical path can be the reset network. That could be one
reason behind the degradation of speed.
One solution is to ignore the reset network in your timing contraints.
This could be done with certain synthesis directives.

I am sure the reset is creating timing failure but Xilinx tools are not
specifying that the problem is due to reset.

I am actually looking for some ideas for creating reset tree and
appropriate buffer for that purpose.

Hope this helps
Sudhi

 

[sudhi]

Xilinx timing report should show you the critical path.
And since your controlled reset is generated using internal registerd
signals, it may be a good option to use the synchronous reset as
general purpose routing resource is used for syncronous resets.

Have a look at this
http://www.xilinx.com/bvdocs/appnotes/xapp119.pdf (search for
"asynchronous") its for a spartan device, you should find similar stuff
for your device.

Sudhi
PS: Xilinx answer database is the best place to get answers!

 

actually an AND of two registered internal signals.
after that i am putting a buf component and then driving the reset of
modules.

Register the AND output.