Request Verification on an issue

[Daku]

Could some Verilog guru please help ? I
have a circuit consisting of two D flip-flops
with reset. Each of these are driven by a separate clock. The 'D'
inputs of both are
held at logic '1'.
The tricky part is the resets. The 'Q' outputs of the two D flip-flops
are fed into a NAND gate, and the output of this NAND gate acts
as the common reset signal for both the two flip-flops. My question
(with reference to the source code files attached below) is:
1. Is the way I am handling this reset signal
the correct one - I am holding the reset value
in a 'wire', and then this is being fed into each
of the 'reset' ports of the two flip-flops. If I try
hold the reset value in a 'reg' I get compilation errors about
continuous assignment.

module dfftb;

reg clock1;
reg clock2;
reg d;
wire resetwire;
wire q1, q1_bar;
wire q2, q2_bar;

initial
begin
$dumpfile ("/root/verilog/dfftb.vcd");
$dumpvars (1, dfftb);
clock1 = 0;
clock2 = 0;
d = 1;
#250 $finish;
end

always
begin
#5 clock1 = !clock1;
end

always
begin
#10 clock2 = !clock2;
end

nand(resetwire, q1, q2);


dff d0(
.d (d),
.clk (clock1),
.reset (resetwire),
.q (q1),
.q_bar (q1_bar)
);

dff d1(
.d (d),
.clk (clock2),
.reset (resetwire),
.q (q2),
.q_bar (q2_bar)
);

endmodule

module dff( d, clk, reset, q, q_bar);
input d;
input clk;
input reset;
output q;
output q_bar;

reg q;
reg q_bar;

always @ (posedge clk or negedge reset)
if(~reset)
begin
q <= 1'b0;
end
else
begin
q <= d;
q_bar <= !d;
end
endmodule

The code compiles and runs fine under Icarus Verilog 0.9.1.

 

[Muzaffer Kal]

On Wed, 14 Apr 2010 21:57:03 -0700 (PDT), Daku <dakupoto@gmail.com>
wrote:

Could some Verilog guru please help ? I
have a circuit consisting of two D flip-flops
with reset. Each of these are driven by a separate clock. The 'D'
inputs of both are
held at logic '1'.
The tricky part is the resets. The 'Q' outputs of the two D flip-flops
are fed into a NAND gate, and the output of this NAND gate acts
as the common reset signal for both the two flip-flops. My question
(with reference to the source code files attached below) is:
1. Is the way I am handling this reset signal
the correct one - I am holding the reset value
in a 'wire', and then this is being fed into each
of the 'reset' ports of the two flip-flops. If I try
hold the reset value in a 'reg' I get compilation errors about
continuous assignment.

You certainly need a wire to connect to the output of the nand gate so
what you're doing is technically correct. The rest of the design is
what doesn't make sense ;-) As is, this circuit doesn't do anything
else. Are these two flops used to synchronize a pulse from one clock
domain to another? If so it's not a safe design as it stands. In a
real application you'll see intermitent errors.

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[Jonathan Bromley]

On Apr 15, 5:57 am, Daku <dakup...@gmail.com> wrote:

Could some Verilog guru please help ?

Your problem is not really about Verilog, it's about
sensible synchronous design...

I have a circuit consisting of two D flip-flops
with reset. Each of these are driven by a separate clock. The 'D'
inputs of both are held at logic '1'.
The tricky part is the resets. The 'Q' outputs of the two D flip-flops
are fed into a NAND gate, and the output of this NAND gate acts
as the common reset signal for both the two flip-flops.

As Muzaffer Kal said much more politely: YUCK!

This is presumably intended to be a which-came-first
discriminator, yes? The critical problem with it is that
there is no way to guarantee that the reset glitch will be
long enough to reset BOTH flops, because as soon as it has
reset just ONE of them it will go away again! Sure it may
work in simulation, because Verilog nonblocking assignment
guarantees that the reset will last for long enough for both
flops to respond to it, but no sane designer would want
such a thing on their chip.

If you have access to a fast clock in the design, you could
use a straightforward state machine to work out what happened.

Otherwise you must resort to other tricks. Whatever you do,
though, will be risky. What happens if the two posedges
happen very close together? Even if your circuit responds
correctly, the resulting who-came-first output pulse could
be arbitrarily short.

Depending on exactly what you're trying to do, it may be
that analogue phase-detection techniques will be better.
Or perhaps the classic phase/frequency detector circuit
(a nasty cross-coupled gates affair that actually works
rather well) might be a good solution. Your two-flop
idea most certainly is not.

You're likely to get a broader range of responses on
comp.arch.fpga.
--
Jonathan Bromley

 

[Cary R.]

Jonathan Bromley wrote:

On Apr 15, 5:57 am, Daku <dakup...@gmail.com> wrote:

Could some Verilog guru please help ?

Your problem is not really about Verilog, it's about
sensible synchronous design...

I'll disagree slightly here. If this is a digital phase detector then
there is no synchronous design and in reality there should be no digital
design either. It's an analog design where the analog simulation tool
can tell you the true linear range, phase noise, reset functionality,
etc. If the assumption is that some digital tool or even worse synthesis
will verify/generate a working circuit then I agree this will likely
lead to disappointment. If it's just a model for other parts of the
digital design to interact with then it should be fine, though I would
spend some time making the model match the real circuit better.

Cary

 

[Daku]

Dear All,
Right now, I am just trying to analyze a
phase frequency detector. There are are several silicon-proven
implementations of
it, for example using S-R flip-flops, D flip-flops, and a very
efficient one that
uses "True Single Phase Clock" and no flip-
flops etc., at all. I am trying to see how
I could replicate the design in Verilog.
Synthesis will come later.



On Apr 16, 9:51 pm, "Cary R." <no-s...@host.spam> wrote:

Jonathan Bromley wrote:
On Apr 15, 5:57 am, Daku <dakup...@gmail.com> wrote:

Could some Verilog guru please help ?

Your problem is not really about Verilog, it's about
sensible synchronous design...

I'll disagree slightly here. If this is a digital phase detector then
there is no synchronous design and in reality there should be no digital
design either. It's an analog design where the analog simulation tool
can tell you the true linear range, phase noise, reset functionality,
etc. If the assumption is that some digital tool or even worse synthesis
will verify/generate a working circuit then I agree this will likely
lead to disappointment. If it's just a model for other parts of the
digital design to interact with then it should be fine, though I would
spend some time making the model match the real circuit better.

Cary