request for help in some verilog syntaxes

Thank you very much for the explanation. Could you please also explain in the following what << operator is doing? I read that it shifts the bits to the left but the operands are integers and not binary numbers so does verilog converts these integers into binary numbers and then perform the shift operation? Is the data width of the result ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7) automatically set to Baud8GeneratorAccWidth + 1? since the result is assigned to Baud8GeneratorInc, which is Baud8GeneratorAccWidth + 1 wide. I am also not able to understand in "Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;" how the lower 18 bits of Baud8GeneratorAcc in the LHS of the above assignment is assigned to 19 bits of Baud8GeneratorAcc in the RHS of above assignment. Please clarify

parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 18; // MJ Use 18 not 16
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];

Thanks