Request for feedback: adding vector types to STANDARD

[Peter Ashenden]

Folks,

The IEEE VHDL Working Group is considering a proposal to add vector types to
the package STANDARD in the next revision of the language. We would like
your feedback on the issue.

Currently, package STANDARD defines types STRING as a vector of CHARACTER
elements, and BIT_VECTOR as a vector of BIT elements. The proposal is to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models, among
other applications.

REAL_VECTOR is defined in STANDARD in the VHDL-AMS standard. Adding it to
the base VHDL standard would enhance portability of packages between the two
languages.

The down side is that there is potential to break existing models. Suppose,
for example, a model declares INTEGER_VECTOR in a package MY_TYPES, and then
uses the package throughout the model with use clauses. If we add
INTEGER_VECTOR to STANDARD, which is used in all design units, we would now
have the same name used from two different packages. The VHDL rules
covering visibility of names would cause neither version to be visible.
Models suffering this effect would have to be edited to remove the
declaration in the user-defined package.

We would appreciate feedback from users on their preferred option: adding
the proposed types to STANDARD, or not adding the types to avoid breaking
legacy models. Rationale for your preference would be helpful. You can
either reply to this newsgroup or to me directly. I'll summarize the
feedback on this group.

Many thanks.

Cheers,

Peter Ashenden

--
Dr. Peter J. Ashenden peter@ashenden.com.au
Ashenden Designs Pty. Ltd. www.ashenden.com.au
PO Box 640 Ph: +61 8 8339 7532
Stirling, SA 5152 Fax: +61 8 8339 2616
Australia Mobile: +61 414 70 9106

 

[rickman]

Peter Ashenden wrote:

Folks,

The IEEE VHDL Working Group is considering a proposal to add vector types to
the package STANDARD in the next revision of the language. We would like
your feedback on the issue.

Currently, package STANDARD defines types STRING as a vector of CHARACTER
elements, and BIT_VECTOR as a vector of BIT elements. The proposal is to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models, among
other applications.

REAL_VECTOR is defined in STANDARD in the VHDL-AMS standard. Adding it to
the base VHDL standard would enhance portability of packages between the two
languages.

The down side is that there is potential to break existing models. Suppose,
for example, a model declares INTEGER_VECTOR in a package MY_TYPES, and then
uses the package throughout the model with use clauses. If we add
INTEGER_VECTOR to STANDARD, which is used in all design units, we would now
have the same name used from two different packages. The VHDL rules
covering visibility of names would cause neither version to be visible.
Models suffering this effect would have to be edited to remove the
declaration in the user-defined package.

We would appreciate feedback from users on their preferred option: adding
the proposed types to STANDARD, or not adding the types to avoid breaking
legacy models. Rationale for your preference would be helpful. You can
either reply to this newsgroup or to me directly. I'll summarize the
feedback on this group.

If the example you gave is the only way in which existing code could
break, I don't see that as a major roadblock. It would be very simple
to pick a new name for use in a model and do a global substitution.
This should be easy to do without affecting the operation of the code.
I know that models have had a lot of work done with them to develop and
debug. But a name change can be done without affecting the code
functionality.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Mike Treseler]

Peter Ashenden wrote:

The proposal is to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models, among
other applications.

That would be a convenience.

The down side is that there is potential to break existing models. Suppose,
for example, a model declares INTEGER_VECTOR in a package MY_TYPES, and then
uses the package throughout the model with use clauses.

I expect that most would find and fix that
soon after the first simulation compile.

We would appreciate feedback from users on their preferred option: adding
the proposed types to STANDARD, or not adding the types to avoid breaking
legacy models.

I would add the types. The odds of tripping over them is small
and recovery is swift for the unlucky.

-- Mike Treseler

 

[Peter Ashenden]

Paul,

The proposed addition is for the sake of convenience (for which you might
read "usability"). This is in the same spirit as providing types such as
BIT_VECTOR, NATURAL, POSITIVE, etc, in package STANDARD. The language
doesn't depend on them being there (as it does for, say, BOOLEAN), but they
are generally useful for users.

As a separate issue, there is a proposal to extend composite types to allow
unconstrained elements. You can find this proposal, along with others, at
www.eda.org/vhdl-200x-ft/. The extended composites proposal is FT-14.

Cheers,

PA

--
Dr. Peter J. Ashenden peter@ashenden.com.au
Ashenden Designs Pty. Ltd. www.ashenden.com.au
PO Box 640 Ph: +61 8 8339 7532
Stirling, SA 5152 Fax: +61 8 8339 2616
Australia Mobile: +61 414 70 9106



"Paul Uiterlinden" <no@spam.nl> wrote in message
news:cprfbk$ot3$1@voyager.news.surf.net...

Peter Ashenden wrote:
Folks,

The IEEE VHDL Working Group is considering a proposal to add vector
types to
the package STANDARD in the next revision of the language. We would
like
your feedback on the issue.

Currently, package STANDARD defines types STRING as a vector of
CHARACTER
elements, and BIT_VECTOR as a vector of BIT elements. The proposal is
to
define vector types for BOOLEAN, INTEGER, REAL and TIME. Users have
commented that these types would be useful for verification models,
among
other applications.

Is this just a matter of convenience or does it really add something
that whould not be possible without it? Is suppose an array (vector) of
an unconstrained type will still not be possible.

Paul.