D
davew
Guest
Hi all,
in my code I use header files with macro definitions to report back the pipeline delay of a given module.
Here is an example:
`define PIPELINE_DELAY_boxcar_filter_parallel(number_of_taps) (clogb2(number_of_taps)*`PIPELINE_DELAY_add + `PIPELINE_DELAY_signed_fixed_point_format_convertor)
So I can change the pipeline delay and definition in the header file of a low level module without breaking things higher up. This works fine but it would be so much nicer if there was a way to do this as part of the language. Is there another way and have I overlooked something in the language? I use Verilog 2001 and have little experience of System Verilog in case that solves my problem in a "nicer" way.
Dave W.
in my code I use header files with macro definitions to report back the pipeline delay of a given module.
Here is an example:
`define PIPELINE_DELAY_boxcar_filter_parallel(number_of_taps) (clogb2(number_of_taps)*`PIPELINE_DELAY_add + `PIPELINE_DELAY_signed_fixed_point_format_convertor)
So I can change the pipeline delay and definition in the header file of a low level module without breaking things higher up. This works fine but it would be so much nicer if there was a way to do this as part of the language. Is there another way and have I overlooked something in the language? I use Verilog 2001 and have little experience of System Verilog in case that solves my problem in a "nicer" way.
Dave W.