Repeatable constraints random generation in SystemVerilog.

[Dwayne Dilbeck]

You can't read in the seed value. You can only set it. The LRM section
dealing with manually setting the Random Seed is located below.

Basically you will always set it at simulation initialization. Each run
will be identical, but the data is random.

Note: the same seed used across tools is not garanteed to produce the same
results. The same results can only be generated in the origianl simulator.



13.14 Manually seeding randomize

Each object maintains its own internal RNG, which is used exclusively by its
randomize() method. This

allows objects to be randomized independent of each other and of calls to
other system randomization functions.

When an object is created, its RNG is seeded using the next value from the
RNG of the thread that creates

the object. This process is called hierarchical object seeding.

Sometimes it is desirable to manually seed an object's RNG using the
srandom() method. This can be done

either in a class method or external to the class definition:

An example of seeding the RNG internally, as a class method, is as follows:

class Packet;

rand bit[15:0] header;

....

function new (int seed);

this.srandom(seed);

....

endfunction

endclass

An example of seeding the RNG externally is as follows:

Packet p = new(200); // Create p with seed 200.

p.srandom(300); // Re-seed p with seed 300.

Calling srandom() in an object's new() function assures the object's RNG is
set with the new seed before

any class member values are randomized.

"humann" <hongqing.hu@gmail.com> wrote in message
news:7952f1cb-727d-44e2-9534-b401de00bdf3@e10g2000prf.googlegroups.com...

Constraints random generation is why I learn SystemVerilog. The test
data is different from time to time
for the same Test Program.
But sometimes, I need to repeat same test data set for debug,
specifically if checker reports a error. How can I do it in
SystemVerilog?
Are there any system function to get "random seed" in SystemVerilog?
Using the same seed can guarantee to reproduce the same test data?
What I what to do is the following pseudo code:

// in checker
if (expected != received)
sned_to_mailbox("ERROR");

// in mailbox
if (get_message == "ERROR")
report_error_msg();
seed = get_random_seed();
write_to_log(seed)

Any other solutions are welcome.

 

[humann]

Constraints random generation is why I learn SystemVerilog. The test
data is different from time to time
for the same Test Program.
But sometimes, I need to repeat same test data set for debug,
specifically if checker reports a error. How can I do it in
SystemVerilog?
Are there any system function to get "random seed" in SystemVerilog?
Using the same seed can guarantee to reproduce the same test data?
What I what to do is the following pseudo code:

// in checker
if (expected != received)
sned_to_mailbox("ERROR");

// in mailbox
if (get_message == "ERROR")
report_error_msg();
seed = get_random_seed();
write_to_log(seed)

Any other solutions are welcome.

 

[karthik]

If you are using VCS, it is very easy to meet your requirement.

By default VCS generates initial random seed and also we can manually
seed at run time using +ntb_random_seed=<value>. And also we can use
+ntb_automatic_random_seed to generate different random seeds at every
run.
Random stability will be maintained as long as the seed value is same.
At instances we need to capture this random seed value to tune the
functionality of the testbench. We have an in-built system function to
meet this requirement.
** You may need latest VCS release to use this system function **
Syntax:
$get_initial_random_seed()
This returns an integer value of random seed.

Use model:
This can be added anywhere inside your testbench code. A simple use
model is to use it inside $display to print the initial random value.

initial
$display("Random seed= %d", $get_initial_random_seed());


Note: This system task will also print manual seed value through
+ntb_random_seed=<value>.

 

[humann]

On Jan 14, 1:32 pm, karthik <karthikeyan.i...@gmail.com> wrote:

If you are using VCS, it is very easy to meet your requirement.

By default VCS generates initial random seed and also we can manually
seed at run time using +ntb_random_seed=<value>. And also we can use
+ntb_automatic_random_seed to generate different random seeds at every
run.
Random stability will be maintained as long as the seed value is same.
At instances we need to capture this random seed value to tune the
functionality of the testbench. We have an in-built system function to
meet this requirement.
** You may need latest VCS release to use this system function **
Syntax:
$get_initial_random_seed()
This returns an integer value of random seed.

Use model:
This can be added anywhere inside your testbench code. A simple use
model is to use it inside $display to print the initial random value.

initial
$display("Random seed= %d", $get_initial_random_seed());

Note: This system task will also print manual seed value through
+ntb_random_seed=<value>.

Thank you for your answer. I use Synopsys VCS. The code works.