Repeat concatenation and Modelsim

D

DW

Guest
Hello,
Can anyone confirm that the Verilog language definition rules out a repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.

Modelsim Altera v5.7e seems to let this pass and produces invalid code.
Quartus II version 3.0 seems to reject the use of this, although I have been
informed that a later release (version 4.0 I believe) allows it (when it
apparently should not).

Although the example given is simplistic, I had used a combination of
defparam'd parameters which produced the 0 repeat. I do not have a complete
language reference (could be a good investment).

Thankyou,
DW.
 
In article <c8vo2c$sq7$1$8300dec7@news.demon.co.uk>, DW wrote:
Can anyone confirm that the Verilog language definition rules out a repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.
Click to expand...
IEEE Std 1364-2001 Version C
4.1.14 Concatenations
....
Another form of concatenation is the replication operation. The
first expression shall be a non-zero, non-X and non-Z constant expression,
the second expression follows the rules for concatenations.
This example replicates "w" 4 times:
{4{w}} // This is equivalent to {w, w, w, w}
....

I have had occasion to wish otherwise, but there you have it.

- Larry
 
Larry Doolittle wrote:
In article <c8vo2c$sq7$1$8300dec7@news.demon.co.uk>, DW wrote:
Can anyone confirm that the Verilog language definition rules out a repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.


IEEE Std 1364-2001 Version C
4.1.14 Concatenations
...
Another form of concatenation is the replication operation. The
first expression shall be a non-zero, non-X and non-Z constant expression,
the second expression follows the rules for concatenations.
This example replicates "w" 4 times:
{4{w}} // This is equivalent to {w, w, w, w}
...

I have had occasion to wish otherwise, but there you have it.
Click to expand...
I've occasionally considered allowing 0 repeat expressions as
an extension to Icarus Verilog, but this gets into the issue of
how to handle 0-bit-width expressions in Verilog in general.
Zero-bit-width expressions are natural mathematically, but kinda
weird in practice, and working out all the consequences would
take some effort by some concientious people.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
--
Dave Wooff
dave@dmwooff.freeserve.co.uk
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message
news:slrncb6rrn.as8.ldoolitt@recycle.lbl.gov...
In article <c8vo2c$sq7$1$8300dec7@news.demon.co.uk>, DW wrote:
Can anyone confirm that the Verilog language definition rules out a
repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.

IEEE Std 1364-2001 Version C
4.1.14 Concatenations
...
Another form of concatenation is the replication operation. The
first expression shall be a non-zero, non-X and non-Z constant expression,
the second expression follows the rules for concatenations.
This example replicates "w" 4 times:
{4{w}} // This is equivalent to {w, w, w, w}
...

I have had occasion to wish otherwise, but there you have it.

- Larry
Click to expand...
Thanks, I too have a use for this but I guess I must work around it.
 
I've used it anyway,and our tools grumble but still work. NC-Verilog
warns you about it and defaults the multiplier to 1, so as long as you
realize that you can (carefully) still use it. It's a necessary evil until
there
is a better way to do parameterized designs....

Mike

"David Wooff" <dave@dmwooff.freeserve.co.uk> wrote in message
news:c90i5e$fb8$1@newsg1.svr.pol.co.uk...
--
Dave Wooff
dave@dmwooff.freeserve.co.uk
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message
news:slrncb6rrn.as8.ldoolitt@recycle.lbl.gov...
In article <c8vo2c$sq7$1$8300dec7@news.demon.co.uk>, DW wrote:
Can anyone confirm that the Verilog language definition rules out a
repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.

IEEE Std 1364-2001 Version C
4.1.14 Concatenations
...
Another form of concatenation is the replication operation. The
first expression shall be a non-zero, non-X and non-Z constant
expression,
the second expression follows the rules for concatenations.
This example replicates "w" 4 times:
{4{w}} // This is equivalent to {w, w, w, w}
...

I have had occasion to wish otherwise, but there you have it.

- Larry

Thanks, I too have a use for this but I guess I must work around it.
Click to expand...
 
"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0405261352.190d2eb8@posting.google.com...
"NewsHound" <newshound@austin.rr.com> wrote in message
news:<P31tc.511$4x2.206@fe2.texas.rr.com>...
I've used it anyway,and our tools grumble but still work. NC-Verilog
warns you about it and defaults the multiplier to 1, so as long as you
realize that you can (carefully) still use it.

Actually, I believe that NC-Verilog produces a 1'b0 for it. This was
what Verilog-XL did for it in non-optimizing mode, so we chose to
regard that as the de facto standard.
Click to expand...
You are right; I forgot to mention that the value of the 1 bit is zero.

Thanks for the clarification.
Mike
 
GPL Cver allows 0 width concats because a user we were not matching XL.
The algorithm is that a 0 repeat count removes the element. It is then
an error if the entire concatenate disappers (i.e. becomes zero width).
Here is the bug report test:

============

module top;
reg [10:0] rf_addr_ext;
reg [10:0] rf_addr;
parameter AW = 5;
parameter DW = 5;
initial begin
rf_addr_ext = {{AW - DW{1'b0}}, rf_addr};
end

endmodule

============

On Tue, 25 May 2004 16:18:38 +0100, DW <dave_wooff@hotmail.com> wrote:
Hello,
Can anyone confirm that the Verilog language definition rules out a repeat
concatenation of 0. i.e.
{0{1'b1}} is NOT allowed.

Modelsim Altera v5.7e seems to let this pass and produces invalid code.
Quartus II version 3.0 seems to reject the use of this, although I have been
informed that a later release (version 4.0 I believe) allows it (when it
apparently should not).

Although the example given is simplistic, I had used a combination of
defparam'd parameters which produced the 0 repeat. I do not have a complete
language reference (could be a good investment).

Thankyou,
DW.
Click to expand...

--
Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402
 
Steve Meyer wrote:
GPL Cver allows 0 width concats because a user we were not matching XL.
The algorithm is that a 0 repeat count removes the element. It is then
an error if the entire concatenate disappers (i.e. becomes zero width).
Here is the bug report test:

============

module top;
reg [10:0] rf_addr_ext;
reg [10:0] rf_addr;
parameter AW = 5;
parameter DW = 5;
initial begin
rf_addr_ext = {{AW - DW{1'b0}}, rf_addr};
end

endmodule
Click to expand...
Actually, as Steve Sharp pointed out in this thread, XL does *NOT*
do it that way. A repeat count of 0 generates a *one* bit wide
expression. I think I like your behavior better, but if your goal
was to match XL behavior, you missed.

It turns out that in your example, it doesn't matter, but it would
be interesting to know what this example does with various tools:

module top
parameter ZERO = 0;
reg [7:0] sample;
initial begin
sample = {4'b1, ZERO{1'b0}, 4'b1};
$display("sample = %b");
end
endmodule

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
 
Stephen Williams <spamtrap@icarus.com> wrote in message news:<40BBA832.6090302@icarus.com>...
Actually, as Steve Sharp pointed out in this thread, XL does *NOT*
do it that way. A repeat count of 0 generates a *one* bit wide
expression. I think I like your behavior better, but if your goal
was to match XL behavior, you missed.
Click to expand...
It isn't quite that simple. What I described was the behavior of XL
with optimizations turned off (+no_speedup). A zero repeat count
behaves differently in XL depending on optimization options. With
one set of options, it behaves differently depending on whether the
value being replicated is a constant or variable. They may in fact
have matched the behavior of XL with a particular set of command
line options on their particular testcase.

I consider the behavior I described as the most "standard" behavior,
because it is what occurs without optimizations, thus avoiding any
obscure bugs in those optimizations. It is the most "vanilla"
behavior. But that isn't the way users generally run the tool.

If XL had demonstrated consistent behavior, that probably would have
been officially standardized. Since it doesn't, it was deemed best
to make a zero repeat count illegal or undefined.

It turns out that in your example, it doesn't matter, but it would
be interesting to know what this example does with various tools:

module top
parameter ZERO = 0;
reg [7:0] sample;
initial begin
sample = {4'b1, ZERO{1'b0}, 4'b1};
$display("sample = %b");
end
endmodule
Click to expand...
You would want to test replicating something like 2'b1x instead.
Otherwise you can't tell whether the tool is producing a 1-bit
zero because it replicated the operand once, or because it
produces a 1-bit value with the MSB or LSB of the operand, or
because it produces a zero with the width of the operand, or
because it produces a 1-bit zero. XL actually does at least
two of these possibilities with different options.
 
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