renoir shift syntax

[dan list]

I was hoping somebody had some insight into what's going on here:

quoting

http://courses.ece.uiuc.edu/ece312/machine_problems/shifting.htm



How to do shifting in VHDL

HDL Designer, for whatever reason, doesn't like standard VHDL shifting syntax.
Like most shortcomings of HDL Designer, though, this can be worked around. Shown
below are some possible way to do shifting in a way that HDL Designer will
accept. Note that these may not be the most elegant, but they work.

In the examples below, SigA gets SigB shifted by SigC places. The examples
assume that SigA, SigB, and SigC are std_logic_vectors, and that SigA and SigB
are the same size.

Shifting left
SigA <= std_logic_vector("sll"(unsigned(SigB), to_integer(unsigned(SigC))));

Shifting right (logical)
SigA <= std_logic_vector("srl"(unsigned(SigB), to_integer(unsigned(SigC))));

Shift right (arithmetic)
COUNT := to_integer(unsigned(SigC(3 downto 0)));
if (SigC(3 downto 0) = "0000") then
SigA <= SigB; --Perform no shifting
else
SigA(15 - COUNT downto 0) := SigB(15 downto COUNT);
SigA(15 downto (15 - COUNT + 1)) := (others => SigB(15));
end if;

Note: COUNT is a variable of type integer, and must be declared earlier in your
VHDL.

If you have found a more elegant way to make shifting work, please e-mail the
head TA with how you did it.

</quoting>

Basically this is weird. I have checked every vhdl93 looking option I can find,
and I still get errors trying to use the standard syntax. Does anybody know what
is going wrong?

Thanks in advance

 

[Mike Treseler]

dan list wrote:

HDL Designer, for whatever reason, doesn't like
standard VHDL shifting syntax. Like most
shortcomings of HDL Designer, though,
this can be worked around.

A better work-around would be to bypass HDL designer completely.
Use your text editor to write code the way you really want it.
Use modelsim to verify the syntax and function of the code.
Finally, use leonardo to synth the code once it sims correctly.

Renoir/HDL designer is one way for the
schematically-oriented to generate VHDL code.
If you already know the language, skip the code generators.

-- Mike Treseler