E
Eric
Guest
Hi me again, Im trying to remove latches from my code but im not sure
how, here is a very simple code (only FSM transition process) to show
what im trying to do:
transition : process(rd_en) is
variable a,b : std_logic_vector(1 downto 0);
begin
case state is
when S0 =>
if rd_en = '1' then
a := datain;
Next_state <= S1;
else
Next_state <= S0;
end if;
when S1 =>
if rd_en = '1' then
b := datain;
Next_state <= S2;
else
NExt_state <= S1;
end if;
when S2 =>
dataout <= a & b;
Next_state <= S0;
when Others =>
dataout <= "0000";
a := "00";
b := "00";
end case;
end process;
ok this is a simplified FSM, what im doing is reading from a RAM into
variables.....which i then output to a 4bit dataout. As i understand
latches will be created for a and b, since their values need to be
stored. Am i wrong?
how, here is a very simple code (only FSM transition process) to show
what im trying to do:
transition : process(rd_en) is
variable a,b : std_logic_vector(1 downto 0);
begin
case state is
when S0 =>
if rd_en = '1' then
a := datain;
Next_state <= S1;
else
Next_state <= S0;
end if;
when S1 =>
if rd_en = '1' then
b := datain;
Next_state <= S2;
else
NExt_state <= S1;
end if;
when S2 =>
dataout <= a & b;
Next_state <= S0;
when Others =>
dataout <= "0000";
a := "00";
b := "00";
end case;
end process;
ok this is a simplified FSM, what im doing is reading from a RAM into
variables.....which i then output to a 4bit dataout. As i understand
latches will be created for a and b, since their values need to be
stored. Am i wrong?