removing inferred tri-state devices?

Hello,

I am in the proccess of creating a synthesized netlist with a very
small (6) cell count in order to test out a new std. cell library.
The RTL code used for synthesized has some inferred tri-state buffers,
which of course, a tri-state isn't one of the cells in the library.
What is the best method to modify the below code so no tri-state
devices will be inferred during synthesis?

....always(@posedge ...)
....
....

assign add_out = out_ptr[0] ? fifo_reg_0 : {fifo_width {1'bz}}; //
HERE => INFERRED TRI-STATE
assign add_out = out_ptr[1] ? fifo_reg_1 : {fifo_width {1'bz}};

...
...
...
Thanks,

Phillip

 

[Mike Lewis]

<phillip.r.prentice@gmail.com> wrote in message
news:1177517099.232473.166390@s33g2000prh.googlegroups.com...

Hello,

I am in the proccess of creating a synthesized netlist with a very
small (6) cell count in order to test out a new std. cell library.
The RTL code used for synthesized has some inferred tri-state buffers,
which of course, a tri-state isn't one of the cells in the library.
What is the best method to modify the below code so no tri-state
devices will be inferred during synthesis?

...always(@posedge ...)
...
...

assign add_out = out_ptr[0] ? fifo_reg_0 : {fifo_width {1'bz}}; //
HERE => INFERRED TRI-STATE
assign add_out = out_ptr[1] ? fifo_reg_1 : {fifo_width {1'bz}};

..
..
..
Thanks,

Phillip

The code snippet is what you would do if you want a tri-state .. as you have
already found.
If you don't want that .. you'll have to replace the 1'bz with something
else .. 1'b0 or 1'b1 or another signal. Or you will have
remove the enable and have add_out = fifo_reg_0.

Mike

 

[Mike Lewis]

"Mike Lewis" <someone@micrsoft.com> wrote in message
news:COWdnW0s_LmsPbLbnZ2dnUVZ_segnZ2d@magma.ca...

phillip.r.prentice@gmail.com> wrote in message
news:1177517099.232473.166390@s33g2000prh.googlegroups.com...
Hello,

I am in the proccess of creating a synthesized netlist with a very
small (6) cell count in order to test out a new std. cell library.
The RTL code used for synthesized has some inferred tri-state buffers,
which of course, a tri-state isn't one of the cells in the library.
What is the best method to modify the below code so no tri-state
devices will be inferred during synthesis?

...always(@posedge ...)
...
...

assign add_out = out_ptr[0] ? fifo_reg_0 : {fifo_width {1'bz}}; //
HERE => INFERRED TRI-STATE
assign add_out = out_ptr[1] ? fifo_reg_1 : {fifo_width {1'bz}};

..
..
..
Thanks,

Phillip


The code snippet is what you would do if you want a tri-state .. as you
have already found.
If you don't want that .. you'll have to replace the 1'bz with something
else .. 1'b0 or 1'b1 or another signal. Or you will have
remove the enable and have add_out = fifo_reg_0.

Mike

or you can also turn it into a case statement

case (out_ptr)
00001 : add_out = fifo_reg_0;
00010 : add_out = fifo_reg_1:
etc
endcase