removing "false" gated clock nets in encounter when fixing D

[mk]

On Thu, 08 Nov 2007 15:48:35 +0100, Thomas Popp
<Thomas.Popp@iaik.tugraz.at> wrote:

Dear all,

I have the following problem:

I use the clock signal as input to a combinational circuit. More
specifically, the clock is connected to an input of a NOR gate and the
output of this gate is feed into the combinational block. The main
difference here to usual "clock gating" is that I'm only interested in
the logic value of the clock and not in its active edges etc.

The only constraint I have is that the clock input pin of the NOR gate
is a leaf pin in the clock tree (so skew etc. is controlled), which can
easily be defined in the clock tree specification file (.ctstch-file).

Still, (parts of) the subsequent combinational block are considered by
encounter as part of the clock tree. This causes some false clock gating
hold check violations, but this can be avoided by disabling the
respective timing arc in the NOR gate (set_disable_timing...).

Until here, everything is fine (sorry for the long story ;-).

The problem starts when I now optimize my design concerning DRVs
(optDesign -setup -drv ...). Here, all these alleged clock gating nets
are excluded from the optimization. If I call e.g. "reportCapViolation",
these nets are marked "C" (= part of clock net). But in my case, this is
wrong. Does anybody have an idea how to solve this issue, i.e. to make
the clock net stop at the NOR gates also for DRV fixing?

I don't have my notes handy now but there is a CTS command which can
mark the input pin of the NOR as a leaf node. If you use it, the cone
of logic following the NOR won't be marked as clock. That should fix
all your problems.

 

[Thomas Popp]

Dear all,

I have the following problem:

I use the clock signal as input to a combinational circuit. More
specifically, the clock is connected to an input of a NOR gate and the
output of this gate is feed into the combinational block. The main
difference here to usual "clock gating" is that I'm only interested in
the logic value of the clock and not in its active edges etc.

The only constraint I have is that the clock input pin of the NOR gate
is a leaf pin in the clock tree (so skew etc. is controlled), which can
easily be defined in the clock tree specification file (.ctstch-file).

Still, (parts of) the subsequent combinational block are considered by
encounter as part of the clock tree. This causes some false clock gating
hold check violations, but this can be avoided by disabling the
respective timing arc in the NOR gate (set_disable_timing...).

Until here, everything is fine (sorry for the long story ;-).

The problem starts when I now optimize my design concerning DRVs
(optDesign -setup -drv ...). Here, all these alleged clock gating nets
are excluded from the optimization. If I call e.g. "reportCapViolation",
these nets are marked "C" (= part of clock net). But in my case, this is
wrong. Does anybody have an idea how to solve this issue, i.e. to make
the clock net stop at the NOR gates also for DRV fixing?

Thanks,
-Thomas Popp

 

[Thomas Popp]

Dear mk,

mk wrote:

I don't have my notes handy now but there is a CTS command which can
mark the input pin of the NOR as a leaf node. If you use it, the cone
of logic following the NOR won't be marked as clock. That should fix
all your problems.

Thanks for you answer. But as I wrote in my initial post, I'm already
defining the input pins of the NOR gates as clock tree leaf nodes (via
the clock tree specification file). CTS is happy with that. However,
during optimization (optDesign -drv ...), the logic gates and nets
following the NORs are still considered part of the clock tree.

When looking through the doc, I didn't find a CTS command you mentioned.
It would be very nice if you could sometime tell me the name of the
command. Maybe setting the leaf pins in this way has more effects
(included the needed one) than only specifying the respective pins in
the clock tree spec file (as "GlobalLeafPin").

Thanks,
-Thomas