Regfile access

S

sebas

Guest
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
if (wr_en)
array_reg [w_addrl <= w_data;
assign r_data = array_reg [r_addr];



why is the writing done sequentially and the reading purely combinational
That is writing inside an always activated on the front edge of clk an
reading in a continuous assignment.

Thanks

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Mar 15, 10:26 am, "sebas"
<tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
        if (wr_en)
                array_reg [w_addrl <= w_data;
assign r_data = array_reg [r_addr];

why is the writing done sequentially and the reading purely combinational?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.
 
On Mar 15, 10:26=A0am, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
=A0 =A0 =A0 =A0 if (wr_en)
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array_reg [w_addrl <=3D w_data;
assign r_data =3D array_reg [r_addr];

why is the writing done sequentially and the reading purel
combinational=
?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Lol, good answer. Let me rephrase that, then: is this a usual practice: th
writing to be synchronous and the reading to be asynchronous? Can they bot
be asynchronous?

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Tue, 15 Mar 2011 17:05:38 -0500, "andreiseb" wrote:

is this a usual practice: the
writing to be synchronous and the reading to be asynchronous? Can they both
be asynchronous?
Click to expand...
Yes, but only if your synthesis tool and target technology
support latches or other memory elements that implement
such functionality.

The phrase "rare as rocking-horse shit" springs to mind.
It used to be fairly common, but it's generally frowned
upon these days in FPGA-land.
--
Jonathan Bromley
 
On Mar 15, 11:05 pm, "andreiseb"
<andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Mar 15, 10:26=A0am, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
=A0 =A0 =A0 =A0 if (wr_en)
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array_reg [w_addrl <=3D w_data;
assign r_data =3D array_reg [r_addr];

why is the writing done sequentially and the reading purely
combinational> >?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.

Lol, good answer. Let me rephrase that, then: is this a usual practice: the
writing to be synchronous and the reading to be asynchronous? Can they both
be  asynchronous?          
Click to expand...
then it would not be a register, it would be a wire :)

think of how a flipflop works

-Lasse
 
On Mar 15, 3:05 pm, "andreiseb"
<andrei.jacota@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Mar 15, 10:26=A0am, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
=A0 =A0 =A0 =A0 if (wr_en)
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array_reg [w_addrl <=3D w_data;
assign r_data =3D array_reg [r_addr];

why is the writing done sequentially and the reading purely
combinational> >?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.

Lol, good answer. Let me rephrase that, then: is this a usual practice: the
writing to be synchronous and the reading to be asynchronous? Can they both
be  asynchronous?          

---------------------------------------        
Posted throughhttp://www.FPGARelated.com- Hide quoted text -

- Show quoted text -
Click to expand...
A register file is basically an array of registers (aka flip/flops)
with a defined width and depth. As an example you could take 128
registers and define them as 8 bits wide and 16 deep. This can define
in Verilog like this:

reg [7:0] my_reg_file [3:0]

The write to the register file must be synchronous, after all they are
registers and they have to save state. In theory it would be possible
to create an asynchronous write, but this is comp.arch.fpga and any
attempt to do so in an FPGA would be a big mistake.

The "read' isn't really a read, but a multiplexer selection of a
single register within the array. In the case of the above example
this would be a eight 16-to-1 mux with 4 select lines. The address to
data would be combinatorial (aka asynchronous), but it would also
include a synchronous path for the clock-to-out from the registers in
the array.

Complicating the asynchronous vs synchronous description of the access
is that the read address would have been generated by something
synchronous and the data out will likely be stored in something
synchronous. So the label is really in the eye of the beholder.

Ed McGettigan
--
Xilinx Inc.
 
Ed McGettigan <ed.mcgettigan@xilinx.com> writes:

On Mar 15, 10:26 am, "sebas"
tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:
snip
why is the writing done sequentially and the reading purely combinational?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks    


Because the designer wanted the read to be asynchronous?
Click to expand...
....so that the synthesizer would infer CLB RAM?

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
 
On Tuesday, March 15, 2011 7:03:37 PM UTC-4, Ed McGettigan wrote:
On Mar 15, 3:05 pm, "andreiseb"
andrei...@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Mar 15, 10:26=A0am, "sebas"
tanarne...@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
=A0 =A0 =A0 =A0 if (wr_en)
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array_reg [w_addrl <=3D w_data;
assign r_data =3D array_reg [r_addr];

why is the writing done sequentially and the reading purely
combinational> > >?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.

Lol, good answer. Let me rephrase that, then: is this a usual practice: the
writing to be synchronous and the reading to be asynchronous? Can they both
be  asynchronous?          

---------------------------------------        
Posted throughhttp://www.FPGARelated.com- Hide quoted text -

- Show quoted text -

A register file is basically an array of registers (aka flip/flops)
with a defined width and depth. As an example you could take 128
registers and define them as 8 bits wide and 16 deep. This can define
in Verilog like this:

reg [7:0] my_reg_file [3:0]
Click to expand...
I think you meant to write:

reg [7:0] my_reg_file [0:15];

if you really wanted 16 8-bit registers
rather than 4 8-bit registers.

The write to the register file must be synchronous, after all they are
registers and they have to save state. In theory it would be possible
to create an asynchronous write, but this is comp.arch.fpga and any
attempt to do so in an FPGA would be a big mistake.

The "read' isn't really a read, but a multiplexer selection of a
single register within the array. In the case of the above example
this would be a eight 16-to-1 mux with 4 select lines. The address to
data would be combinatorial (aka asynchronous), but it would also
include a synchronous path for the clock-to-out from the registers in
the array.

Complicating the asynchronous vs synchronous description of the access
is that the read address would have been generated by something
synchronous and the data out will likely be stored in something
synchronous. So the label is really in the eye of the beholder.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
 
On Mar 16, 2:35 pm, Gabor <ga...@alacron.com> wrote:
On Tuesday, March 15, 2011 7:03:37 PM UTC-4, Ed McGettigan wrote:
On Mar 15, 3:05 pm, "andreiseb"
andrei...@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On Mar 15, 10:26=A0am, "sebas"
tanarne...@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote:
Hi,

A newbie's question, in the following code:

module reg_file
(
input wire clk,
input wire wr_en,
input wire [1:0] w_addr, r_addr,
input wire [7:O] w_data,
output wire [7:Ol r_data
)

reg [7:Ol array_reg [2**1:0] ;
always @(posedge clk)
=A0 =A0 =A0 =A0 if (wr_en)
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 array_reg [w_addrl <=3D w_data;
assign r_data =3D array_reg [r_addr];

why is the writing done sequentially and the reading purely
combinational> > > >?
That is writing inside an always activated on the front edge of clk and
reading in a continuous assignment.

Thanks =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Because the designer wanted the read to be asynchronous?

Ed McGettigan
--
Xilinx Inc.

Lol, good answer. Let me rephrase that, then: is this a usual practice: the
writing to be synchronous and the reading to be asynchronous? Can they both
be  asynchronous?          

---------------------------------------        
Posted throughhttp://www.FPGARelated.com-Hide quoted text -

- Show quoted text -

A register file is basically an array of registers (aka flip/flops)
with a defined width and depth.  As an example you could take 128
registers and define them as 8 bits wide and 16 deep.  This can define
in Verilog like this:

reg [7:0] my_reg_file [3:0]

I think you meant to write:

reg [7:0] my_reg_file [0:15];

if you really wanted 16 8-bit registers
rather than 4 8-bit registers.



The write to the register file must be synchronous, after all they are
registers and they have to save state.  In theory it would be possible
to create an asynchronous write, but this is comp.arch.fpga and any
attempt to do so in an FPGA would be a big mistake.

The "read' isn't really a read, but a multiplexer selection of a
single register within the array.  In the case of the above example
this would be a eight 16-to-1 mux with 4 select lines.  The address to
data would be combinatorial (aka asynchronous), but it would also
include a synchronous path for the clock-to-out from the registers in
the array.

Complicating the asynchronous vs synchronous description of the access
is that the read address would have been generated by something
synchronous and the data out will likely be stored in something
synchronous.  So the label is really in the eye of the beholder.

Ed McGettigan
--
Xilinx Inc.- Hide quoted text -

- Show quoted text -- Hide quoted text -

- Show quoted text -
Click to expand...
A quick google search for Verliog example code shows that Gabor is
100% correct. I've probably only used arrays a handful of times and
didn't realize that right hand vector was an integer range (which I
find a bit odd, but there must be some underlying elegance to be
described this way).

Ed McGettigan
--
Xilinx Inc.
 
On Wednesday, March 16, 2011 8:33:45 PM UTC-4, Ed McGettigan wrote:
On Mar 16, 2:35 pm, Gabor <ga...@alacron.com> wrote:
[snip]
A register file is basically an array of registers (aka flip/flops)
with a defined width and depth.  As an example you could take 128
registers and define them as 8 bits wide and 16 deep.  This can define
in Verilog like this:

reg [7:0] my_reg_file [3:0]

I think you meant to write:

reg [7:0] my_reg_file [0:15];

if you really wanted 16 8-bit registers
rather than 4 8-bit registers.
[snip]

A quick google search for Verliog example code shows that Gabor is
100% correct. I've probably only used arrays a handful of times and
didn't realize that right hand vector was an integer range (which I
find a bit odd, but there must be some underlying elegance to be
described this way).

Ed McGettigan
--
Xilinx Inc.
Click to expand...
I'm not sure why you find it odd. The range of
a bit vector is an "integer range". If you
want 16 bits you write

reg [15:0] foo;

So if you want 16 registers why would you
think you would write something other than

reg [15:0] foo [0:15];
or (less common)
reg [15:0] foo [15:0];

I'm not sure why the range is usually ascending
on the right side. Since you can't access
a sub-range of vectors, it really doesn't affect
the resulting hardware regardless of its direction.
However the fact that the range defines 16 items
rather than the range of the required address
(Log2(16)) seems normal to me.

-- Gabor
 
On Mar 17, 6:21 am, Gabor <ga...@alacron.com> wrote:
On Wednesday, March 16, 2011 8:33:45 PM UTC-4, Ed McGettigan wrote:
On Mar 16, 2:35 pm, Gabor <ga...@alacron.com> wrote:
[snip]
A register file is basically an array of registers (aka flip/flops)
with a defined width and depth.  As an example you could take 128
registers and define them as 8 bits wide and 16 deep.  This can define
in Verilog like this:

reg [7:0] my_reg_file [3:0]

I think you meant to write:

reg [7:0] my_reg_file [0:15];

if you really wanted 16 8-bit registers
rather than 4 8-bit registers.
[snip]

A quick google search for Verliog example code shows that Gabor is
100% correct.  I've probably only used arrays a handful of times and
didn't realize that right hand vector was an integer range (which I
find a bit odd, but there must be some underlying elegance to be
described this way).

Ed McGettigan
--
Xilinx Inc.

I'm not sure why you find it odd.  The range of
a bit vector is an "integer range".  If you
want 16 bits you write

 reg [15:0] foo;

So if you want 16 registers why would you
think you would write something other than

 reg [15:0] foo [0:15];
or (less common)
 reg [15:0] foo [15:0];

I'm not sure why the range is usually ascending
on the right side.  Since you can't access
a sub-range of vectors, it really doesn't affect
the resulting hardware regardless of its direction.
However the fact that the range defines 16 items
rather than the range of the required address
(Log2(16)) seems normal to me.

-- Gabor- Hide quoted text -

- Show quoted text -
Click to expand...
The reason why I found it odd that the same text seemed to create two
different ranges depending on the usage.

[15:0] = 16 bits = Range of 65535 to 0 (if on the left)
[15:0] = 16 elements = Range of 15 to 0 (if on the right)

As I typed the above I saw why it is the way that it is, but my mind
keeps trying to go back to the binary to (unsigned) integer conversion
for the range....

Ed McGettigan
--
Xilinx Inc.
 
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
(snip on register file in verilog)

The reason why I found it odd that the same text seemed to create two
different ranges depending on the usage.

[15:0] = 16 bits = Range of 65535 to 0 (if on the left)
[15:0] = 16 elements = Range of 15 to 0 (if on the right)

As I typed the above I saw why it is the way that it is, but my mind
keeps trying to go back to the binary to (unsigned) integer conversion
for the range....
Click to expand...
I wonder if you are a Pascal programmer. Pascal has a subrange type
where you specify the range of values that you would like it
to have.

PL/I allows one to specify the number of bits (for BINARY types),
or decimal digits (for DECIMAL types). (and note that the
underlying representation doesn't have to agree.)

Fortran has SELECTED_INT_KIND() and SELECTED_REAL_KIND that
allow one to specify in decimal digits (even though it is
usually implemented in binary) the range one needs.

But if you think of them as bit patterns, instead of numerical
values, then it is more obvious to count bits.

-- glen
 
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