Regarding Synchronization of multiple control signals

[jas]

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.


The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.


The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.


I have to design an interface where the control signals from the
processor to my interface will be


1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase. (From processor to Design )
2. LWE it is a read and write signal single bit active low. (From
processor to Design )
3. LOE Output enable active low (From processor to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor to Design )
6. LAD data 32 bits (Bidirectional)


I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .


I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .


My Confusion is that when we have multiple control signal passing the
clock domain . Can we synchronize with 2 flops all the control
signals.


Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.


In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.


I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.


Any suggestion ideas will be highly appreciated


Thanks


Vipul

 

[steve ravet]

Vipul, this is a pretty standard and common problem in FPGAs. You
can't independently synchronize a bunch of control signals when
crossing clock domains. They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain. You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers. The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals. By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase.  (From processor  to Design )
2. LWE it is a read and write signal single bit active low. (From
processor  to Design )
3. LOE Output enable active low  (From processor  to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor  to Design )
6. LAD data 32 bits  (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .

My Confusion is that when we have multiple control signal passing the
clock  domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

 

[rickman]

Good advice. If the bus logic works like a typical async memory
interface, he doesn't need to resync everything for metastability.
There are either one or two timing control strobes depending on the
details of the signals or how you wish to use them. You may be able
to use either LALE or LCS as the single timing control or you may want
to use LWE and LOE as a mutually exclusive pair of timing control
strobes. Pick which way you want to do this based on the details of
the timing from the CPU.

Sync the timing control to your FPGA clock domain and detect the
appropriate edge. Use this as a register enable for grabbing the
address and data (on writes). The LOE will be used to enable the
output drivers onto the LAD bus for reads.

This is not a complex design, but how you do it depends on the details
of the bus protocol and timing specs. It may be that you don't need
to register the address/data or any of the other control signals at
all.

Rick


On Oct 15, 5:48 pm, steve ravet <steve.ra...@gmail.com> wrote:

Vipul, this is a pretty standard and common problem in FPGAs.  You
can't independently synchronize a bunch of control signals when
crossing clock domains.  They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain.  You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers.  The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals.  By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase.  (From processor  to Design )
2. LWE it is a read and write signal single bit active low. (From
processor  to Design )
3. LOE Output enable active low  (From processor  to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor  to Design )
6. LAD data 32 bits  (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .

My Confusion is that when we have multiple control signal passing the
clock  domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

 

[Vips]

On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote:

Vipul, this is a pretty standard and common problem in FPGAs.  You
can't independently synchronize a bunch of control signals when
crossing clock domains.  They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain.  You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers.  The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals.  By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase.  (From processor  to Design )
2. LWE it is a read and write signal single bit active low. (From
processor  to Design )
3. LOE Output enable active low  (From processor  to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor  to Design )
6. LAD data 32 bits  (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .

My Confusion is that when we have multiple control signal passing the
clock  domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

Hi Rick /Steve

Thanks for your reply. The processor might send continuous data and i
don't have the control for the processor. In handshake mechanism the
processor might have to see my response then send the next data. Rick
you are right that we can use LOE for read case to latch data in the
LAD bus. All signals are mutually exclusive and it is typically like a
async memory interface.

I have googled but did dot get any good relevant text on this that
talk about async memory interface . All talk about CDC issues and
control and data bus synchronization. I am looking for some thing on
async memory interface or something that is async and have to be
synchronized at the interface to be used by other logic in the design.
I will look into it the way you both have advised.

Thanks

Vipul

 

[rickman]

On Oct 16, 10:55 am, Vips <thevipulsi...@gmail.com> wrote:

On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote:



Vipul, this is a pretty standard and common problem in FPGAs. You
can't independently synchronize a bunch of control signals when
crossing clock domains. They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain. You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers. The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals. By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase. (From processor to Design )
2. LWE it is a read and write signal single bit active low. (From
processor to Design )
3. LOE Output enable active low (From processor to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor to Design )
6. LAD data 32 bits (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .

My Confusion is that when we have multiple control signal passing the
clock domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

Hi Rick /Steve

Thanks for your reply. The processor might send continuous data and i
don't have the control for the processor. In handshake mechanism the
processor might have to see my response then send the next data. Rick
you are right that we can use LOE for read case to latch data in the
LAD bus. All signals are mutually exclusive and it is typically like a
async memory interface.

I have googled but did dot get any good relevant text on this that
talk about async memory interface . All talk about CDC issues and
control and data bus synchronization. I am looking for some thing on
async memory interface or something that is async and have to be
synchronized at the interface to be used by other logic in the design.
I will look into it the way you both have advised.

Thanks

Vipul

I doubt that you will find much on how to design your circuit. This
is very basic and you just need to understand the timing and function
of the control signals. Just keep in mind that many signals won't
need to be registered at all if they are stable at the time they are
needed and only control signals need to be double registered for
metastability. If you need any real help, drop me an email and send
me details of your bus and FPGA interface.

Rick

 

[Gabor]

On Oct 17, 3:55 pm, rickman <gnu...@gmail.com> wrote:

On Oct 16, 10:55 am, Vips <thevipulsi...@gmail.com> wrote:



On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote:

Vipul, this is a pretty standard and common problem in FPGAs.  You
can't independently synchronize a bunch of control signals when
crossing clock domains.  They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain.  You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers.  The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals.  By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase.  (From processor  to Design )
2. LWE it is a read and write signal single bit active low. (From
processor  to Design )
3. LOE Output enable active low  (From processor  to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor  to Design )
6. LAD data 32 bits  (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain ..

My Confusion is that when we have multiple control signal passing the
clock  domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

Hi Rick /Steve

Thanks for your reply. The processor might send continuous data and i
don't have the control for the processor. In handshake mechanism the
processor might have to see my response then send the next data. Rick
you are right that we can use LOE for read case to latch data in the
LAD bus. All signals are mutually exclusive and it is typically like a
async memory interface.

I have googled but did dot get any good relevant text on this that
talk about async memory interface . All talk about CDC issues and
control and data bus synchronization. I am looking for some thing on
async memory interface or something that is async and have to be
synchronized at the interface to be used by other logic in the design.
I will look into it the way you both have advised.

Thanks

Vipul

I doubt that you will find much on how to design your circuit.  This
is very basic and you just need to understand the timing and function
of the control signals.  Just keep in mind that many signals won't
need to be registered at all if they are stable at the time they are
needed and only control signals need to be double registered for
metastability.  If you need any real help, drop me an email and send
me details of your bus and FPGA interface.

Rick

One other reason to register all of the data pins as well as the
control
lines is to get a delay pipeline. Then you can do things like find
the
trailing edge of the strobe signal and latch the data from three clock
cycles ago.

Regards,
Gabor

 

[steve ravet]

On Oct 16, 9:55 am, Vips <thevipulsi...@gmail.com> wrote:

On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote:





Vipul, this is a pretty standard and common problem in FPGAs.  You
can't independently synchronize a bunch of control signals when
crossing clock domains.  They'll all cross individually OK, but
there's no guarantee that they'll all end up in the same clock phase
on the other side, especially if the destination domain is faster than
the source domain.  You need to have a send/receive handshake that
consists of a single signal, synchronized in both directions.

The control signals that need to cross are flopped directly in the
receiving domain without any synchronizers.  The handshake signal is
double flop synchronized and used as an enable on the flops that
receive the control signals.  By the time the double flopped sync
signals make it through to the flop enable, the other control signals
are stable and can be safely latched.

An async FIFO is another possibility.

Do a search on clock domain crossing and you'll come up with plenty of
answers.

--steve

On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote:

Hi Everyone,

I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.

The motoroll Processor will have LBC Local bus controller signals
will
be comunicating to my interface inside the FPGA.

The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.

I have to design an interface where the control signals from the
processor to my interface will be

1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase.  (From processor  to Design )
2. LWE it is a read and write signal single bit active low. (From
processor  to Design )
3. LOE Output enable active low  (From processor  to Design )
4. LCS is active low signal from processor to my interface. It is
used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor  to Design )
6. LAD data 32 bits  (Bidirectional)

I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference
clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .

I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .

My Confusion is that when we have multiple control signal passing the
clock  domain . Can we synchronize with 2 flops all the control
signals.

Shall we use some glue logic to make sure we pass and synchronise
only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that
are
input to a latch and sampled when we get the synchronized signal.

In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.

I am using 3X clock in the destination clock domain and has ample
time
to sample the signal in the interface block.

Any suggestion ideas will be highly appreciated

Thanks

Vipul

Hi Rick /Steve

Thanks for your reply. The processor might send continuous data and i
don't have the control for the processor. In handshake mechanism the
processor might have to see my response then send the next data. Rick
you are right that we can use LOE for read case to latch data in the
LAD bus. All signals are mutually exclusive and it is typically like a
async memory interface.

I have googled but did dot get any good relevant text on this that
talk about async memory interface . All talk about CDC issues and
control and data bus synchronization. I am looking for some thing on
async memory interface or something that is async and have to be
synchronized at the interface to be used by other logic in the design.
I will look into it the way you both have advised.

Thanks

Vipul

Hi Vipul, I'm not familiar with that interface but if it has a valid/
ready type of handshake with the slave then those are the signals that
will be double flopped. Valid from the master is double flopped
before it gets to the slave, and ready is double flopped from the
slave back to the master. That way all of the control or data has
crossed safely to the slave before the master is allowed to proceed.

If there's no handshake, and the master sends data without waiting for
a response from the slave then you may have to go with an async fifo,
which has one port in the receiving domain and one port in the sending
domain. If you're using relatively recent FPGAs then the block RAMs
may incorporate the logic needed for an async FIFO, which gets rid of
any CDC considerations from your design. Then the only concern is
that the receiving end be able to keep up with the sending end, since
the slave has no way of holding off the master. I think you said your
slave runs 3x faster than your master so you may already have that
problem solved.

 

[Chris Maryan]

You can do all sorts of tricks with synchronizing, but it really boils
down to one of two cases:

- Synchronous: You should have the bus clock coming from the CPU run
into your FPGA, then do everything synchronously on a bus clock domain
in the FPGA. To interface to the main logic, you can use an internal
FIFO to your main clock domain (or any number of other methods -
google "clock domain crossing"). This is the "right" (and possibly
only) way to do it if you want to utilize the full bandwidth to the
bus.

- Asynchronous: Most (possibly all?) Motorolla/Freescale processors
have programmable bus timing on their external parallel bus. You can
set the timing to give you tons of setup/hold time to allow you to
take a snapshot of the data/address lines after the skew has worked
itself out. The idea is that you design your FPGA logic to capture the
LCS signal through a dual flip flop synchronizer, wait i.e. 10 FPGA
clock cycles, then capture the address/data (by which time the data
would be stable). The idea is that only one signal is ever dealt with
asynchronously (LCS).

Chris