Regarding passing a control signal from fast to slow cloak d

V

Vips

Guest
Hello All ,

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.

Any experience and Ideas will be highly appreciated.

thanks

Vips
 
Hello All ,

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.

Any experience and Ideas will be highly appreciated.
Click to expand...
I suggest that you read Mike Stein's article: "Crossing the abyss
asynchronous signals in a synchronous world" from July 24, 2003 issue o
EDN magazine,
URL: http://www.edn.com/article/CA310388.html



---------------------------------------
Posted through http://www.FPGARelated.com
 
On Feb 16, 9:03 am, Vips <thevipulsi...@gmail.com> wrote:

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch"  the pulse in the slow domain to get
it sampled.
Click to expand...
Use it to enable a toggle flip-flop in the 100MHz domain.
Then you have a step-edge that you can resample in
your 12MHz clock domain.

Obviously this won't work if the 100MHz pulse happens
more often than about 6MHz, because you'll need at least
two samples in the 12MHz domain to resynchronize and
detect the edge (probably three, for comfort and simplicity).
If that's the case then you may need to mess around with
Gray counters. (Actually the toggle FF is a degenerate
case of a Gray counter, with just one bit.)

If the 100MHz and 12.5MHz clocks are in fact synchronous
(e.g. using a DCM) then the same toggle-to-stretch
technique works well, but the resynchronization problem
is slightly different - details depend on exactly how the
two clocks are related. It's often simpler just to assume
that they are unrelated, to save yourself the bother of
worrying about those details.

Jonathan Bromley
 
On 2/16/2011 9:03 AM, Vips wrote:
Hello All ,

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.

Any experience and Ideas will be highly appreciated.

thanks

Vips
Click to expand...
Dear Vips,
Design your system with only a 100MHz clock. Make a signal which is high
for one in eight cycles of the 100MHz clock. Use this to clock enable
all the FFs in what used to be your 12.5MHz domain.
HTH. Syms.
 
There is a paper at Sunburst Design called Clock Domain Crossing (CDC
Design & Verification which may be of some help.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
"Vips" <thevipulsinha@gmail.com> wrote in message
news:b95be8ab-c3fd-47a0-bd00-ac0f3a73c9de@o7g2000prn.googlegroups.com...
Hello All ,

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.

Any experience and Ideas will be highly appreciated.

thanks

Vips
Click to expand...
Do it this way (this is the basic idea, neater with a strobed system, plus
look after the possible SR conflict)

http://tinypic.com/r/10zo1ow/7

Phil
 
"Jonathan Bromley" <spam@oxfordbromley.plus.com> wrote in message
news:d375c296-7ed3-4d21-a33f-fcd6c8169934@z20g2000yqe.googlegroups.com...
On Feb 16, 9:03 am, Vips <thevipulsi...@gmail.com> wrote:

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.
Click to expand...
Use it to enable a toggle flip-flop in the 100MHz domain.
Then you have a step-edge that you can resample in
your 12MHz clock domain.

Obviously this won't work if the 100MHz pulse happens
more often than about 6MHz, because you'll need at least
two samples in the 12MHz domain to resynchronize and
detect the edge (probably three, for comfort and simplicity).
If that's the case then you may need to mess around with
Gray counters. (Actually the toggle FF is a degenerate
case of a Gray counter, with just one bit.)

If the 100MHz and 12.5MHz clocks are in fact synchronous
(e.g. using a DCM) then the same toggle-to-stretch
technique works well, but the resynchronization problem
is slightly different - details depend on exactly how the
two clocks are related. It's often simpler just to assume
that they are unrelated, to save yourself the bother of
worrying about those details.

Jonathan Bromley


Jeez! Is this was thinking in HDL does for you?
See my other post!

Phil
 
On 2/16/2011 5:11 PM, Phil Jessop wrote:
"Jonathan Bromley"<spam@oxfordbromley.plus.com> wrote in message
news:d375c296-7ed3-4d21-a33f-fcd6c8169934@z20g2000yqe.googlegroups.com...
On Feb 16, 9:03 am, Vips<thevipulsi...@gmail.com> wrote:

I am designing a system where I have to transfer a control pulse
signal from 100 MHz to 12.5 MHz. The pulse signal is a clock wide in
100 MHz domain. How to "Stretch" the pulse in the slow domain to get
it sampled.

Use it to enable a toggle flip-flop in the 100MHz domain.
Then you have a step-edge that you can resample in
your 12MHz clock domain.

Obviously this won't work if the 100MHz pulse happens
more often than about 6MHz, because you'll need at least
two samples in the 12MHz domain to resynchronize and
detect the edge (probably three, for comfort and simplicity).
If that's the case then you may need to mess around with
Gray counters. (Actually the toggle FF is a degenerate
case of a Gray counter, with just one bit.)

If the 100MHz and 12.5MHz clocks are in fact synchronous
(e.g. using a DCM) then the same toggle-to-stretch
technique works well, but the resynchronization problem
is slightly different - details depend on exactly how the
two clocks are related. It's often simpler just to assume
that they are unrelated, to save yourself the bother of
worrying about those details.

Jonathan Bromley


Jeez! Is this was thinking in HDL does for you?
See my other post!

Phil


Nope, this is was [sic] thinking in terms of a newsgroup post does for
Click to expand...
you. Next year, when that link to your lovely picture has gone dead,
your archived post will be useless.
HTH, Syms.
 
I think you can miss a pulse with your circuit if you go metastable on the output of the slow FF.

With the T FF (or with pulse stretching) on the fast side followed by some FFs and an edge detect on the slow side, you can put in as many FFs as you like on the slow side to deal with metastability.

Chris
 
On 2/16/2011 7:52 PM, Chris Maryan wrote:
I think you can miss a pulse with your circuit if you go metastable on the output of the slow FF.

With the T FF (or with pulse stretching) on the fast side followed by some FFs and an edge detect on the slow side, you can put in as many FFs as you like on the slow side to deal with metastability.

Chris
Click to expand...
Hi Chris,

At 100MHz, you've got up to 10ns for the metastability to resolve. You
might want to worry about your circuit being hit by a meteorite or taken
by 'The Rapture' before concerning yourself about that type of
metastability event.

Cheers, Syms.

http://www.xilinx.com/support/documentation/application_notes/xapp094.pdf
 
On Wed, 16 Feb 2011 17:11:04 -0000, "Phil Jessop" wrote:

Jeez! Is this was thinking in HDL does for you?
See my other post!s
Click to expand...
Errrm, no, it's what thinking about some of the possible
hidden assumptions and pitfalls may do for you. Something
that does not appear to have much troubled your thinking
in schematic :)
--
Jonathan Bromley
 
100MHz has nothing to do with it - 12.5MHz in the authors orignal question kind of does, but then this circuit isn't generally applicable to clock crossings at higher speeds. Consider if the right FF is followed by combinatorial logic before another FF. If that path has relatively little slack, then a metastable event on the first slow FF will cause a timing violation on the second slow FF. Then the even may be double counted or missed. You can make a assumption reasonably that this you'll never have this little slack at 12.5 MHz, but for the general case it's a problem.

Also, metastability events can and do happen reasonably often.

Chris
 
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