Regarding NRZ

[guest]

Hi everyone, <BR>
Iam basic to the communication design, <BR>
I have a query regarding NRZ interface with FPGA, <p>Can we provide NRZ interface to FPGA, <BR>
how does the voltage level will be at the interface ? <BR>
Is it like 1 --&gt; + V <BR>
&amp;nbsp;0 --&gt; -V ? <BR>
Is it possible to interface it with FPGA? <p>Thanks in Advance.

 

[Falk Brunner]

&lt;guest&gt; schrieb im Newsbeitrag news:ee7e625.-1@WebX.sUN8CHnE...

Hi everyone,
Iam basic to the communication design,
I have a query regarding NRZ interface with FPGA,
Can we provide NRZ interface to FPGA,
how does the voltage level will be at the interface ?
Is it like 1 --&gt; + V
0 --&gt; -V ?
Is it possible to interface it with FPGA?
Thanks in Advance.

This is not a question of NRZ, ist a quaestion of signaling voltage level.

TTL 0-5V
LVTTL 0-3.3V
RS232 +/-12V
etc.

So the FPGA can only output/input voltage levels stated in the datasheet.

--
Regards
Falk

 

[H. Peter Anvin]

Followup to: &lt;bducne$10r362$1@ID-84877.news.dfncis.de&gt;
By author: "Falk Brunner" &lt;Falk.Brunner@gmx.de&gt;
In newsgroup: comp.arch.fpga

guest&gt; schrieb im Newsbeitrag news:ee7e625.-1@WebX.sUN8CHnE...
Hi everyone,
Iam basic to the communication design,
I have a query regarding NRZ interface with FPGA,
Can we provide NRZ interface to FPGA,
how does the voltage level will be at the interface ?
Is it like 1 --&gt; + V
0 --&gt; -V ?
Is it possible to interface it with FPGA?
Thanks in Advance.

This is not a question of NRZ, ist a quaestion of signaling voltage level.

TTL 0-5V
LVTTL 0-3.3V
RS232 +/-12V
etc.

So the FPGA can only output/input voltage levels stated in the datasheet.

Well, it sort of is. NRZ is a trivoltage code (which, I have to
admit, I have never seen the point of... it seems that MFM or
Manchester code is better in every aspect including being
self-synchronizing regardless of the bit sequence. Yet NRZ got used
in USB. Sigh.)

So the question really is:

"Are there any FPGAs with NRZ-capable I/O buffers?"

The answer to the best of my knowledge is "no", but as you said, look
a the data sheets to find what kind of signalling standards your
particular FPGA supports.

Obviously, one can always use an external I/O buffer.

-hpa
--
&lt;hpa@transmeta.com&gt; at work, &lt;hpa@zytor.com&gt; in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

 

[guest]

Dear Falk &amp; Peter, <BR>
&amp;nbsp;&amp;nbsp;&amp;nbsp;Thanks for replying, As Iam basic to this information, Please correct me if iam wromg <p>NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used <BR>
and for transmitting '0' -V volt is used. <p> we have signalling standards like LVTTL, TTL, CMOS they represent '1' as +V and '0' as 0V <p>What do i say the chip, which provides the NRZ interface, <BR>
&amp;nbsp;&amp;nbsp;&amp;nbsp;1) Its signalling varies from +v to -v doesn't return to 0V <BR>
&amp;nbsp;&amp;nbsp;&amp;nbsp;2) Or it has used NRZ coding over Some (say CMOS) signalling standard then one is represented by + Vdd and zero is represented by 0V, am I wright..? <p>3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0 across the physical link ? <p>Thanks in Advance

 

[Falk Brunner]

&lt;guest&gt; schrieb im Newsbeitrag news:ee7e625.2@WebX.sUN8CHnE...

Dear Falk &amp; Peter,
Thanks for replying, As Iam basic to this information, Please correct me
if iam wromg
NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used
and for transmitting '0' -V volt is used.

Yes, this is right, BUT it seems you confuse an electrical IO-standard with
an logic data encoding scheme.

we have signalling standards like LVTTL, TTL, CMOS they represent '1' as
+V and '0' as 0V
What do i say the chip, which provides the NRZ interface,
1) Its signalling varies from +v to -v doesn't return to 0V
2) Or it has used NRZ coding over Some (say CMOS) signalling standard
then one is represented by + Vdd and zero is represented by 0V, am I

wright..?

Yes, you can easyly use a CMOS IO-buffer for NRZ. As well as for Manchaster,
CMI, RZ, NRZI. Again, dont mix up electrical IO-standards with encoding
schemes.

3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0
across the physical link ?

Yes, NRZ is a line coding (the simples you can imagine). It is absolutely
independent on the physical representation. al LOGIC "1" can be 5V, 3.3V,
20mA, +15V etc. where a logic "0" can be 0V, 0mA, -15V etc.

--
Regards
Falk

 

[Uwe Bonnes]

guest &lt;&gt; wrote:
: Dear Falk &amp; Peter, <BR>
: &amp;nbsp;&amp;nbsp;&amp;nbsp;Thanks for replying, As Iam basic to this information,
: Please correct me if iam wromg <p>NRZ coding say it doesn't return to
: 0v. For transmitting '1' +V is used <BR>

: and for transmitting '0' -V volt is used. <p> we have signalling standards
: like LVTTL, TTL, CMOS they represent '1' as +V and '0' as 0V <p>What do i
: say the chip, which provides the NRZ interface, <BR>

: &amp;nbsp;&amp;nbsp;&amp;nbsp;1) Its signalling varies from +v to -v doesn't return to
: 0V <BR>
: &amp;nbsp;&amp;nbsp;&amp;nbsp;2) Or it has used NRZ coding over Some (say CMOS)
: signalling standard then one is represented by + Vdd and zero is represented
: by 0V, am I wright..? <p>3) what is NRZ, is it not an line coding, i.e how
: to represent the 1 and 0 across the physical link ? <p>Thanks in Advance

Could you please post in ASCII and not in HTML. Especially as a "guest",
please keep to the habits.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[rickman]

guest wrote:

Dear Falk &amp; Peter,
Thanks for replying, As Iam basic to this information, Please
correct me if iam wromg

NRZ coding say it doesn't return to 0v. For transmitting '1' +V is
used
and for transmitting '0' -V volt is used.

we have signalling standards like LVTTL, TTL, CMOS they represent '1'
as +V and '0' as 0V

What do i say the chip, which provides the NRZ interface,
1) Its signalling varies from +v to -v doesn't return to 0V
2) Or it has used NRZ coding over Some (say CMOS) signalling
standard then one is represented by + Vdd and zero is represented by
0V, am I wright..?

3) what is NRZ, is it not an line coding, i.e how to represent the 1
and 0 across the physical link ?

Thanks in Advance

You need to do some web searches and learn what NRZ really is. First of
all, NRZ is not one coding style, but it is several which have one
common feature, "the signal does not have to return to zero for each
bit". This refers to the way that the two voltage levels are used to
indicate if a bit is a 1 or a 0, not what the voltage levels are.

So you can use NRZ with TTL signals of 0 volts and 5 volts or you can
use NRZ with RS-232 voltage levels which are +12 volts and -12 volts.

It has been too long since I worked with NRZ and the many variations to
explain it without making an error. So you need to do a little digging
on your own. Do a search on NRZ and possibly also Manchester and any
others that you can think of.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX