M
Mr. Ken
Guest
I was aware that setting this attribute will cause some flip-flops
to share transistors thus reduce power & area. Is this technique
valid in current 130/90nm processes? For example TSMC/Fujitsu/UMC.
I referred some PDF files of the library but unable to find any information.
to share transistors thus reduce power & area. Is this technique
valid in current 130/90nm processes? For example TSMC/Fujitsu/UMC.
I referred some PDF files of the library but unable to find any information.