Regarding High impedance synthesis logic

[Navneet Acharya]

Hi !

I simulated a decoder which has some inputs in high impedence state
it's working fine but i am not getting how will it detect high impedance
state of input during synthesis?
I am using following behavioural statement:

always @(in)
begin
s=1'b0;//select signal or control signal
if(in==1'b0 ||in==1'b1) //detecting whether input is in hi/lo te
begin
s=1'b1;
end
end
Can nebody help me ,I shall be thankful to you.

Regards,
Navneet acharya
M.Tech(VLSI & Embedded System )

 

[Jon Beniston]

navneetacharya@gmail.com (Navneet Acharya) wrote in message news:<49218687.0409061135.404e7f60@posting.google.com>...

Hi !

I simulated a decoder which has some inputs in high impedence state
it's working fine but i am not getting how will it detect high impedance
state of input during synthesis?

You can't implement this.

I am using following behavioural statement:

always @(in)
begin
s=1'b0;//select signal or control signal
if(in==1'b0 ||in==1'b1) //detecting whether input is in hi/lo te
begin
s=1'b1;
end
end

This will just be synthesized to:

assign s = 1'b1;

Best regards,
Jon

 

[Swapnajit Mittra]

navneetacharya@gmail.com (Navneet Acharya) wrote in message news:<49218687.0409061135.404e7f60@posting.google.com>...

Hi !

I simulated a decoder which has some inputs in high impedence state
it's working fine but i am not getting how will it detect high impedance
state of input during synthesis?
I am using following behavioural statement:

always @(in)
begin
s=1'b0;//select signal or control signal
if(in==1'b0 ||in==1'b1) //detecting whether input is in hi/lo te
begin
s=1'b1;
end
end
Can nebody help me ,I shall be thankful to you.

Regards,
Navneet acharya
M.Tech(VLSI & Embedded System )

Hello,

If I have understood your question correctly, you want to
decode (which, by definition, is to generate 2^n outputs
from n inputs) when one or more of the n inputs are in
high impedance state (1'bz).

If this is the case, **for simulation purposes only** take
a look into the casez statement of Verilog. 'casez' has
some pitfalls, so use it with caution.

For synthesis, you essentially need to formulate a priority
decoding method, where you would ignore if an input is
1'bz and use it if and only if it is 1'b1 or 1'b0.

HTH,
- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>

 

[glen herrmannsfeldt]

Swapnajit Mittra wrote:

(snip)

If I have understood your question correctly, you want to
decode (which, by definition, is to generate 2^n outputs
from n inputs) when one or more of the n inputs are in
high impedance state (1'bz).

If this is the case, **for simulation purposes only** take
a look into the casez statement of Verilog. 'casez' has
some pitfalls, so use it with caution.

For synthesis, you essentially need to formulate a priority
decoding method, where you would ignore if an input is
1'bz and use it if and only if it is 1'b1 or 1'b0.

I have recently seen two ICs which have three level inputs.

Look at the Cypress CY7B991 for example.

http://www.cypress.com/cfuploads/img/products/cy7b991992.pdf

It seems such inputs can be pulled to Vcc, Ground or left floating,
where they float somewhere between Vcc and ground, allowing three
input values per pin instead of just two.

I have seen gates with tri-state outputs used to drive such
inputs, allowing all three input levels to be used.
One could simulate this with the 1`bZ state, I suppose.

-- glen

 

[Allan Herriman]

On Tue, 07 Sep 2004 12:01:14 -0700, glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

Swapnajit Mittra wrote:

(snip)

If I have understood your question correctly, you want to
decode (which, by definition, is to generate 2^n outputs
from n inputs) when one or more of the n inputs are in
high impedance state (1'bz).

If this is the case, **for simulation purposes only** take
a look into the casez statement of Verilog. 'casez' has
some pitfalls, so use it with caution.

For synthesis, you essentially need to formulate a priority
decoding method, where you would ignore if an input is
1'bz and use it if and only if it is 1'b1 or 1'b0.

I have recently seen two ICs which have three level inputs.

Look at the Cypress CY7B991 for example.

http://www.cypress.com/cfuploads/img/products/cy7b991992.pdf

It seems such inputs can be pulled to Vcc, Ground or left floating,
where they float somewhere between Vcc and ground, allowing three
input values per pin instead of just two.

I have seen gates with tri-state outputs used to drive such
inputs, allowing all three input levels to be used.
One could simulate this with the 1`bZ state, I suppose.

The MAX6651 has a 4 state input pin: VCC, GND, open, 10k resistor to
ground.

This is expensive to do (and was done in this case to avoid using a
larger package) as it involves a bunch of resistors and comparators.
It is almost certainly not what the OP wants to do.

Regards,
Allan

 

[Swapnajit Mittra]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<chl0cq$1am$1@gnus01.u.washington.edu>...

Swapnajit Mittra wrote:

(snip)

If I have understood your question correctly, you want to
decode (which, by definition, is to generate 2^n outputs
from n inputs) when one or more of the n inputs are in
high impedance state (1'bz).

If this is the case, **for simulation purposes only** take
a look into the casez statement of Verilog. 'casez' has
some pitfalls, so use it with caution.

For synthesis, you essentially need to formulate a priority
decoding method, where you would ignore if an input is
1'bz and use it if and only if it is 1'b1 or 1'b0.

I have recently seen two ICs which have three level inputs.

Look at the Cypress CY7B991 for example.

http://www.cypress.com/cfuploads/img/products/cy7b991992.pdf

It seems such inputs can be pulled to Vcc, Ground or left floating,
where they float somewhere between Vcc and ground, allowing three
input values per pin instead of just two.

I have seen gates with tri-state outputs used to drive such
inputs, allowing all three input levels to be used.
One could simulate this with the 1`bZ state, I suppose.

-- glen

The Cypress chip (and many others in its category - clock skew
generators, PLLs, VCOs etc.) are not binary digital logic
circuit that Verilog can handle (I use 'binary' as opposed
to many-valued logic, which are realizable in hardware
since mid 60s for them and 'digital logic' as opposed to mixed
signal domain). While they are obviously useful, they belong
to separate black art as mastered by Bob Peas and alike. For
Verilog synthesis, we must conform to the rules of the game
- no z and x detection in synthesis.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>

 

[glen herrmannsfeldt]

Swapnajit Mittra wrote:

gah@ugcs.caltech.edu> wrote in message news:<chl0cq$1am$1@gnus01.u.washington.edu>...

(snip)

I have seen gates with tri-state outputs used to drive such
inputs, allowing all three input levels to be used.
One could simulate this with the 1`bZ state, I suppose.

The Cypress chip (and many others in its category - clock skew
generators, PLLs, VCOs etc.) are not binary digital logic
circuit that Verilog can handle (I use 'binary' as opposed
to many-valued logic, which are realizable in hardware
since mid 60s for them and 'digital logic' as opposed to mixed
signal domain).

Yes, they are in a different category. It was interesting to me
that the question came up when only last week I learned about
the Cypress chip, and also one other using three level inputs.

There was also discussion some years ago about using four level
inputs to carry two bits between chips using half as many pins
as binary signals.

After considering for so long that digital circuits couldn't
detect 1`bZ, it is interesting to see a case where they can.

-- glen

 

[Swapnajit Mittra]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<chqlv3$t6d$1@gnus01.u.washington.edu>...

Swapnajit Mittra wrote:

gah@ugcs.caltech.edu> wrote in message news:<chl0cq$1am$1@gnus01.u.washington.edu>...

(snip)

I have seen gates with tri-state outputs used to drive such
inputs, allowing all three input levels to be used.
One could simulate this with the 1`bZ state, I suppose.

The Cypress chip (and many others in its category - clock skew
generators, PLLs, VCOs etc.) are not binary digital logic
circuit that Verilog can handle (I use 'binary' as opposed
to many-valued logic, which are realizable in hardware
since mid 60s for them and 'digital logic' as opposed to mixed
signal domain).

Yes, they are in a different category. It was interesting to me
that the question came up when only last week I learned about
the Cypress chip, and also one other using three level inputs.

There was also discussion some years ago about using four level
inputs to carry two bits between chips using half as many pins
as binary signals.

After considering for so long that digital circuits couldn't
detect 1`bZ, it is interesting to see a case where they can.

-- glen

Perhaps it is just a semantics, but I would not consider them
as 'digital circuits'. A digital circuit, IMHO, does not
employ a passive (active/inactive) element like a capacitor.

On a slightly different topic, many-valued logics are around
for a while. Particularly 4-value (quarternary?) logic was
a hot research topic in until early eighties. The mathematics
behind the subject is, of course, solid (Godel/Łukasiewicz
logic matrix), but in the reality show of hardware, where
it hit the brick wall was the error rate due to the noise.
Still, some circuits were commercially made using many-valued
logic (that worked correctly), among them, IIRC, was a memory
chip from Intel (or was it AMD?) in early 90s.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>