regarding generics in a test bench.....with example .....

[madmax]

Hello
My question is:
How do i declare a generic in a test bench for a std_logic_vector
signal?
like I know we pass a generic value throug a component or entity
instance by generic map.... but how do i declare the 'n' generic in a
test bench??

you can understand by what i mean through the following VHDL code for
an n bit full adder and its vhdl test bench...
The adder is perfect, gets synthesized perfectly, but the problem is
the test bench....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity adderwa is
generic (n: positive:=4);
port(a,b:in std_logic_vector(n-1 downto 0);
cin:in std_logic;
sum: out std_logic_vector(n-1 downto 0);
cout: out std_logic);
end adderwa;

architecture Behavioral of adderwa is

signal result:unsigned(n downto 0);
signal carry:unsigned(n downto 0);
constant zeroes:unsigned(n-1 downto 0):=(others=>'0');
begin

carry<=(zeroes & cin);
result<= carry + ('0' & unsigned(a)) + ('0' & unsigned(b));
cout<= result;
sum<=std_logic_vector(result(n-1 downto 0));
end Behavioral;


here comes the killer... the test bench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity tester is
end entity tester;

architecture behav of tester is

component adderwa is
generic (n: positive:=4);
port(a,b:in std_logic_vector(n-1 downto 0);
cin:in std_logic;
sum: out std_logic_vector(n-1 downto 0);
cout: out std_logic);
end component;

signal t_a: std_logic_vector(n-1 downto 0);
signal t_b: std_logic_vector(n-1 downto 0);
signal t_sum: std_logic_vector(n-1 downto 0);
signal t_cin, t_cout: std_logic;

begin
g1: adderwa generic map(n=>4)
port map(a=>t_a,
b=>t_b,
cin =>t_cin,
sum =>t_sum,
cout=>t_cout);
t_a<="0001";
t_b<="0110";
t_cin<='0';

end architecture behav;


I get the following errors in the test bench compilation


ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 70.
Undefined symbol 'n'.
ERROR:HDLParsers:1209 - "C:/Xilinx92i/tp/adderwa.vhd" Line 70. n:
Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 77.
Undefined symbol 't_a'.
ERROR:HDLParsers:1209 - "C:/Xilinx92i/tp/adderwa.vhd" Line 77. t_a:
Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 78.
Undefined symbol 't_b'.
ERROR:HDLParsers:1209 - "C:/Xilinx92i/tp/adderwa.vhd" Line 78. t_b:
Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 80.
Undefined symbol 't_sum'.
ERROR:HDLParsers:1209 - "C:/Xilinx92i/tp/adderwa.vhd" Line 80. t_sum:
Undefined symbol (last report in this block)
ERROR:HDLParsers:851 - "C:/Xilinx92i/tp/adderwa.vhd" Line 76. Formal a
of adderwa with no default value must be associated with an actual
value.
-->

Total memory usage is 145168 kilobytes

Number of errors : 9 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)


Process "Synthesize" failed




Now::
Firstly... i have defined t_a as a std_logic_vector signal...... still
why does the synthesizer say that signal t_a not defined....

plus I want to know how should I declare a generic in the test bench
for the signals
t_a: std_logic_vector(range n-1 to 0)

how do i declare the above 'n' ........

thank you

 

[Brian Drummond]

On Sat, 4 Oct 2008 15:46:53 -0700 (PDT), madmax <psharma1984@gmail.com>
wrote:

Hello
My question is:
How do i declare a generic in a test bench for a std_logic_vector
signal?
like I know we pass a generic value throug a component or entity
instance by generic map.... but how do i declare the 'n' generic in a
test bench??

Within an architecture it's not a generic, it's a constant.

here comes the killer... the test bench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity tester is
end entity tester;

architecture behav of tester is

constant n : positive := 4;
-- or put all your useful constant and subtype declarations in a package
-- and use it wherever you want

component adderwa is
generic (n: positive:= n);

-- first "n" is component's generic; second ties it to the constant
-- generic (nositive) -- or, just name the generic... see below

port(a,b:in std_logic_vector(n-1 downto 0);
);
end component;

signal t_a: std_logic_vector(n-1 downto 0);
-- now this works because n (the constant) is visible

-- so the errors about undeclared signals go away too

begin
g1: adderwa generic map(n=>n)

-- you don't need to set the value of the generic both here and in the
-- component declaration; but it doesn't hurt

port map(a=>t_a,
b=>t_b,
);

end architecture behav;

ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 70.
Undefined symbol 'n'.
because it WAS undefined in the architecture...
ERROR:HDLParsers:3312 - "C:/Xilinx92i/tp/adderwa.vhd" Line 77.
Undefined symbol 't_a'.
which caused the signal declarations to disappear!

- Brian