regarding error "Range must be bouded by constant expression

Hello everyone...Iam a starter to verilog...While i was doing this program i encountered with the error "Range must be bouded by constant expressions" ....
Please suggest some way to get out from this error....the program is as follows....
module prenorm ( clk,
numsign,
numint,
numfrac,

ieeesign,
ieeeexp,
ieeemant,
ieeeop);

integer i;
input clk;
input numsign;
input [22:0] numint;
input [22:0] numfrac;
reg count;
output reg ieeesign;
output reg [7:0] ieeeexp;
output reg [22:0] ieeemant;
output reg [31:0] ieeeop;
always @(numint or numfrac)
begin
begin : BIT_DET
for (i=22;i>0;i=i-1)
begin
if (numint==1'b1)
begin
count=i;
disable BIT_DET;
end
end
end
ieeesign <= numsign ;
ieeeexp [7:0] <= 127+i;
ieeemant[22:0] <= { numint[count-1:0] , numfrac[22:count] } ;
ieeeop [31:0] <= { ieeesign, ieeeexp , ieeemant[22:0] } ;
end
endmodule