regarding error "Range must be bouded by constant expressio

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Hello everyone...Iam a starter to verilog...While i was doing this program i encountered with the error "Range must be bouded by constant expressions" ....
Please suggest some way to get out from this error....the program is as follows....
module prenorm ( clk,
numsign,
numint,
numfrac,
ieeesign,
ieeeexp,
ieeemant,
ieeeop);
integer i;
input clk;
input numsign;
input [22:0] numint;
input [22:0] numfrac;
output reg ieeesign;
output reg [7:0] ieeeexp;
output reg [22:0] ieeemant;
output reg [31:0] ieeeop;
always @(numint or numfrac)
begin
begin : BIT_DET
for (i=22;i>0;i=i-1)
begin
if (numint==1'b1)
begin

ieeesign <= numsign ;
ieeeexp [7:0] <= 127+i;
ieeemant[22:0] <= { numint[i-1:0] , numfrac[22:i] } ;
ieeeop [31:0] <= { ieeesign, ieeeexp , ieeemant[22:0] } ;
disable BIT_DET;
end
end
end
end
endmodule
 
On 1/5/2013 7:18 AM, venu.chitta1992@gmail.com wrote:
Hello everyone...Iam a starter to verilog...While i was doing this program i encountered with the error "Range must be bouded by constant expressions" ....
Please suggest some way to get out from this error....the program is as follows....
module prenorm ( clk,
numsign,
numint,
numfrac,
ieeesign,
ieeeexp,
ieeemant,
ieeeop);
integer i;
input clk;
input numsign;
input [22:0] numint;
input [22:0] numfrac;
output reg ieeesign;
output reg [7:0] ieeeexp;
output reg [22:0] ieeemant;
output reg [31:0] ieeeop;
always @(numint or numfrac)
begin
begin : BIT_DET
for (i=22;i>0;i=i-1)
begin
if (numint==1'b1)
begin

ieeesign <= numsign ;
ieeeexp [7:0] <= 127+i;
ieeemant[22:0] <= { numint[i-1:0] , numfrac[22:i] } ;
ieeeop [31:0] <= { ieeesign, ieeeexp , ieeemant[22:0] } ;
disable BIT_DET;
end
end
end
end
endmodule

Aparently this is the line causing the problem:


ieeemant[22:0] <= { numint[i-1:0] , numfrac[22:i] } ;

You cannot have a variable range (like [i-1:0]) in Verilog. Clearly the
sum of the two ranges in this statement is a constant, but the syntax
still doesn't allow this. You will need to rewrite this statement as
a loop, like:

integer j;
.. . .
for (j = 0;j <= 22;j = j + 1)
ieeemant[j] <= j <= (22 - i) ? numfrac[i+j] : numint[i+j-23];

Note that the loop operates on one bit at a time, making the
problem of variable range size go away.

Also I would suggest placing the integer declarations for i and j
inside the named process like:

begin : BIT_DET
integer i, j;
for (i=22;i>0;i=i-1)

-- Gabor
 

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