Regarding error in XILINX "Non-constant loop condition not s

Iam encountering an error while simulating in xilinx but it is compiled and simulated in modelsim.In xilinx its showing an error like "Non-constant loop condition not supported for while".So please give some suggestions to remove the error...by the way am a starter to verilog and please do help me out from this error.....

module prenorm( clk,
num1,
num2,
ieeesigna,
ieeeexpa,
sum
);
integer i;
input clk;
input[31:0] num1;
input [31:0]num2;
output reg [0:0] ieeesigna;
output reg [7:0] ieeeexpa;
output reg [22:0] sum;
reg [0:0] ieeesign1;
reg [0:0] ieeesign2;
reg [22:0] ieeemant1;
reg [22:0] ieeemant2;
reg [7:0] ieeeexp1;
reg [7:0] ieeeexp2;
reg [7:0] expdif;
reg [0:0] count;
always @ ( num1 or num2)
begin
ieeesign1 = num1[31];
ieeeexp1 = num1[30:23];
ieeemant1 = num1[22:0];
ieeesign2 = num2[31];
ieeeexp2 = num2[30:23];
ieeemant2 = num2[22:0];
if (ieeeexp1<ieeeexp2)

expdif = ieeeexp2-ieeeexp1;
while (expdif)
begin
ieeemant1 = ieeemant1>>1;
ieeeexp1 = ieeeexp1+1;
expdif = expdif-1;
end

if (ieeeexp2<ieeeexp1)

expdif = ieeeexp1-ieeeexp2;
while (expdif)

begin
ieeemant2 = ieeemant2>>1;
ieeeexp2 = ieeeexp2+1;
expdif = expdif-1;
end

{count,sum} = ieeemant1+ieeemant2;
if (count==1)
begin
{count,sum} = {count,sum} >> 1;
ieeeexp2 = ieeeexp2+1;
end
ieeesigna = ieeesign1;
ieeeexpa =ieeeexp1;
end
endmodule

 

[Mark Curry]

In article <f4e997fa-2986-4de4-ac96-b81cc1c2f66e@googlegroups.com>,
<venu.chitta1992@gmail.com> wrote:

Iam encountering an error while simulating in xilinx but it is compiled and
simulated in modelsim.In xilinx its showing an error like "Non-constant loop
condition not supported for while".So please give some suggestions to
remove the error...by the way am a starter to verilog and please do help me
out from this error.....

<snip code>

This is a fairly common error for new users to Hardware Design Languages.

All loops in your design must be able to be statically defined (i.e. "unrolled"
in software optimzation speak) at COMPILE time.

You're describing hardware not software. Modelsim simulates it fine,
yes, but once you're running through XST you're limited to only
describing behaviour which can be made into hardware.

Think about it a bit, and if you need more details, reply.

Some HDL users suggest not using loops AT ALL in designs intended
for synthesis. Now IMHO, "never" is too extreme, but for new users,
it's a good rule of thumb - don't use them. They may be required
in some circumstances, but it's a more rare exception, not the rule,
and you better be aware of what you're doing.

Regards,

Mark

 

[Gabor]

On 1/14/2013 1:40 PM, venu.chitta1992@gmail.com wrote:

Iam encountering an error while simulating in xilinx but it is compiled and simulated in modelsim.In xilinx its showing an error like "Non-constant loop condition not supported for while".So please give some suggestions to remove the error...by the way am a starter to verilog and please do help me out from this error.....

module prenorm( clk,
num1,
num2,
ieeesigna,
ieeeexpa,
sum
);
integer i;
input clk;
input[31:0] num1;
input [31:0]num2;
output reg [0:0] ieeesigna;
output reg [7:0] ieeeexpa;
output reg [22:0] sum;
reg [0:0] ieeesign1;
reg [0:0] ieeesign2;
reg [22:0] ieeemant1;
reg [22:0] ieeemant2;
reg [7:0] ieeeexp1;
reg [7:0] ieeeexp2;
reg [7:0] expdif;
reg [0:0] count;
always @ ( num1 or num2)
begin
ieeesign1 = num1[31];
ieeeexp1 = num1[30:23];
ieeemant1 = num1[22:0];
ieeesign2 = num2[31];
ieeeexp2 = num2[30:23];
ieeemant2 = num2[22:0];
if (ieeeexp1<ieeeexp2)

expdif = ieeeexp2-ieeeexp1;
while (expdif)
begin
ieeemant1 = ieeemant1>>1;
ieeeexp1 = ieeeexp1+1;
expdif = expdif-1;
end

if (ieeeexp2<ieeeexp1)

expdif = ieeeexp1-ieeeexp2;
while (expdif)

begin
ieeemant2 = ieeemant2>>1;
ieeeexp2 = ieeeexp2+1;
expdif = expdif-1;
end

{count,sum} = ieeemant1+ieeemant2;
if (count==1)
begin
{count,sum} = {count,sum} >> 1;
ieeeexp2 = ieeeexp2+1;
end
ieeesigna = ieeesign1;
ieeeexpa =ieeeexp1;
end
endmodule


You can't do "while" loops in synthesis. The only reasonable loops

are of the form:

for (i = 0; i < N; i = i + 1) // N must be a constant

or any equivalent that always gives the same number of iterations.

That does not mean that you can't have conditions in the loop. For
example if you know that in the worst case case your "while" loop
can iterate 24 times, you can design a loop of 24 iterations, and
then use an "if" statement to make sure it only actually operates on
the signals when the original "while" condition is true.

As others pointed out, however this sort of coding practice can
result in very large and inefficient logic. If you don't actually
need everything in the loop to occur in a single clock cycle you
should code it with an signal as the loop variable to implement
it sequentially.

In the code you posted previously, you had a "disable" statement
which would also cause the loop to vary in the number of iterations,
even though it was a "for" loop in the form that normally works.
You could code that such that instead of disabling the process,
you set a flag that prevents any action during the remaining iterations
of the loop.

-- Gabor

 

On Tuesday, January 15, 2013 8:46:40 AM UTC+5:30, Gabor wrote:

On 1/14/2013 1:40 PM, venu.chitta1992@gmail.com wrote:

Iam encountering an error while simulating in xilinx but it is compiled and simulated in modelsim.In xilinx its showing an error like "Non-constant loop condition not supported for while".So please give some suggestions to remove the error...by the way am a starter to verilog and please do help me out from this error.....



module prenorm( clk,

num1,

num2,

ieeesigna,

ieeeexpa,

sum

);

integer i;

input clk;

input[31:0] num1;

input [31:0]num2;

output reg [0:0] ieeesigna;

output reg [7:0] ieeeexpa;

output reg [22:0] sum;

reg [0:0] ieeesign1;

reg [0:0] ieeesign2;

reg [22:0] ieeemant1;

reg [22:0] ieeemant2;

reg [7:0] ieeeexp1;

reg [7:0] ieeeexp2;

reg [7:0] expdif;

reg [0:0] count;

always @ ( num1 or num2)

begin

ieeesign1 = num1[31];

ieeeexp1 = num1[30:23];

ieeemant1 = num1[22:0];

ieeesign2 = num2[31];

ieeeexp2 = num2[30:23];

ieeemant2 = num2[22:0];

if (ieeeexp1<ieeeexp2)



expdif = ieeeexp2-ieeeexp1;

while (expdif)

begin

ieeemant1 = ieeemant1>>1;

ieeeexp1 = ieeeexp1+1;

expdif = expdif-1;

end



if (ieeeexp2<ieeeexp1)



expdif = ieeeexp1-ieeeexp2;

while (expdif)



begin

ieeemant2 = ieeemant2>>1;

ieeeexp2 = ieeeexp2+1;

expdif = expdif-1;

end



{count,sum} = ieeemant1+ieeemant2;

if (count==1)

begin

{count,sum} = {count,sum} >> 1;

ieeeexp2 = ieeeexp2+1;

end

ieeesigna = ieeesign1;

ieeeexpa =ieeeexp1;

end

endmodule





You can't do "while" loops in synthesis. The only reasonable loops

are of the form:



for (i = 0; i < N; i = i + 1) // N must be a constant



or any equivalent that always gives the same number of iterations.



That does not mean that you can't have conditions in the loop. For

example if you know that in the worst case case your "while" loop

can iterate 24 times, you can design a loop of 24 iterations, and

then use an "if" statement to make sure it only actually operates on

the signals when the original "while" condition is true.



As others pointed out, however this sort of coding practice can

result in very large and inefficient logic. If you don't actually

need everything in the loop to occur in a single clock cycle you

should code it with an signal as the loop variable to implement

it sequentially.



In the code you posted previously, you had a "disable" statement

which would also cause the loop to vary in the number of iterations,

even though it was a "for" loop in the form that normally works.

You could code that such that instead of disabling the process,

you set a flag that prevents any action during the remaining iterations

of the loop.



-- Gabor

Thank you for your reply Gabor....and
Yeah....i used disable statement in my previous post and to my surprise the error in xilinx "disable is not supported" is gone when i changed the device in xilinx....???
Can u please tell me with an example if possible that how can i deal with such variables in the loops.....

 

Iam encountering an error while simulating in xilinx but it is compiled and

simulated in modelsim.In xilinx its showing an error like "Non-constant loop

condition not supported for while".So please give some suggestions to

remove the error...by the way am a starter to verilog and please do help me

out from this error.....



snip code



This is a fairly common error for new users to Hardware Design Languages.



All loops in your design must be able to be statically defined (i.e. "unrolled"

in software optimzation speak) at COMPILE time.



You're describing hardware not software. Modelsim simulates it fine,

yes, but once you're running through XST you're limited to only

describing behaviour which can be made into hardware.



Think about it a bit, and if you need more details, reply.



Some HDL users suggest not using loops AT ALL in designs intended

for synthesis. Now IMHO, "never" is too extreme, but for new users,

it's a good rule of thumb - don't use them. They may be required

in some circumstances, but it's a more rare exception, not the rule,

and you better be aware of what you're doing.



Regards,



Mark

Thank you for your reply mark....
Yes can you please tell me with an example if possible that how can i deal with such variables in a loop with out using conditional statements.....

 

[Mark Curry]

In article <8f43d84e-9ac2-4f98-ad58-64f8d3b1d3a8@googlegroups.com>,
<venu.chitta1992@gmail.com> wrote:

Iam encountering an error while simulating in xilinx but it is compiled and
simulated in modelsim.In xilinx its showing an error like "Non-constant loop
condition not supported for while".So please give some suggestions to
remove the error...by the way am a starter to verilog and please do help me
out from this error.....


snip code

This is a fairly common error for new users to Hardware Design Languages.

All loops in your design must be able to be statically defined (i.e. "unrolled"
in software optimzation speak) at COMPILE time.

You're describing hardware not software. Modelsim simulates it fine,
yes, but once you're running through XST you're limited to only
describing behaviour which can be made into hardware.

Think about it a bit, and if you need more details, reply.

Some HDL users suggest not using loops AT ALL in designs intended
for synthesis. Now IMHO, "never" is too extreme, but for new users,
it's a good rule of thumb - don't use them. They may be required
in some circumstances, but it's a more rare exception, not the rule,
and you better be aware of what you're doing.

Thank you for your reply mark....
Yes can you please tell me with an example if possible that how can i deal with
such variables in a loop with out using conditional statements.....

As Gabor mentioned in the other thread - you must change it to a fixed length
loop WITH conditionals for your terminating conditions.

Look at your code - given any possible input - what is the maximum number of
iterations through the loop that is possible? Now change the
loop to be a fixed length loop with this maximum iteration. Add conditionals
inside the loop to either do the operation or skip it based on your
inputs and loop index.

You can't create HW on the fly. The HW must exist to support the worst
case input stimulus.

And after you manage to do this, you're going to be forced to take a step
back and reevaluate after you see the results. It'll work - but run at 10s
of MHz at best...

Regards,

Mark

 

On Tuesday, January 15, 2013 12:10:22 AM UTC+5:30, venu.ch...@gmail.com wrote:

Iam encountering an error while simulating in xilinx but it is compiled and simulated in modelsim.In xilinx its showing an error like "Non-constant loop condition not supported for while".So please give some suggestions to remove the error...by the way am a starter to verilog and please do help me out from this error.....



module prenorm( clk,

num1,

num2,

ieeesigna,

ieeeexpa,

sum

);

integer i;

input clk;

input[31:0] num1;

input [31:0]num2;

output reg [0:0] ieeesigna;

output reg [7:0] ieeeexpa;

output reg [22:0] sum;

reg [0:0] ieeesign1;

reg [0:0] ieeesign2;

reg [22:0] ieeemant1;

reg [22:0] ieeemant2;

reg [7:0] ieeeexp1;

reg [7:0] ieeeexp2;

reg [7:0] expdif;

reg [0:0] count;

always @ ( num1 or num2)

begin

ieeesign1 = num1[31];

ieeeexp1 = num1[30:23];

ieeemant1 = num1[22:0];

ieeesign2 = num2[31];

ieeeexp2 = num2[30:23];

ieeemant2 = num2[22:0];

if (ieeeexp1<ieeeexp2)



expdif = ieeeexp2-ieeeexp1;

while (expdif)

begin

ieeemant1 = ieeemant1>>1;

ieeeexp1 = ieeeexp1+1;

expdif = expdif-1;

end



if (ieeeexp2<ieeeexp1)



expdif = ieeeexp1-ieeeexp2;

while (expdif)



begin

ieeemant2 = ieeemant2>>1;

ieeeexp2 = ieeeexp2+1;

expdif = expdif-1;

end



{count,sum} = ieeemant1+ieeemant2;

if (count==1)

begin

{count,sum} = {count,sum} >> 1;

ieeeexp2 = ieeeexp2+1;

end

ieeesigna = ieeesign1;

ieeeexpa =ieeeexp1;

end

endmodule

okay...i got you MARK....thank you...

 

On Tuesday, January 15, 2013 12:10:22 AM UTC+5:30, venu.ch...@gmail.com wrote:

Iam encountering an error while simulating in xilinx but it is compiled and simulated in modelsim.In xilinx its showing an error like "Non-constant loop condition not supported for while".So please give some suggestions to remove the error...by the way am a starter to verilog and please do help me out from this error.....



module prenorm( clk,

num1,

num2,

ieeesigna,

ieeeexpa,

sum

);

integer i;

input clk;

input[31:0] num1;

input [31:0]num2;

output reg [0:0] ieeesigna;

output reg [7:0] ieeeexpa;

output reg [22:0] sum;

reg [0:0] ieeesign1;

reg [0:0] ieeesign2;

reg [22:0] ieeemant1;

reg [22:0] ieeemant2;

reg [7:0] ieeeexp1;

reg [7:0] ieeeexp2;

reg [7:0] expdif;

reg [0:0] count;

always @ ( num1 or num2)

begin

ieeesign1 = num1[31];

ieeeexp1 = num1[30:23];

ieeemant1 = num1[22:0];

ieeesign2 = num2[31];

ieeeexp2 = num2[30:23];

ieeemant2 = num2[22:0];

if (ieeeexp1<ieeeexp2)



expdif = ieeeexp2-ieeeexp1;

while (expdif)

begin

ieeemant1 = ieeemant1>>1;

ieeeexp1 = ieeeexp1+1;

expdif = expdif-1;

end



if (ieeeexp2<ieeeexp1)



expdif = ieeeexp1-ieeeexp2;

while (expdif)



begin

ieeemant2 = ieeemant2>>1;

ieeeexp2 = ieeeexp2+1;

expdif = expdif-1;

end



{count,sum} = ieeemant1+ieeemant2;

if (count==1)

begin

{count,sum} = {count,sum} >> 1;

ieeeexp2 = ieeeexp2+1;

end

ieeesigna = ieeesign1;

ieeeexpa =ieeeexp1;

end

endmodule

Okay...i got you Mark...thank you but i had another doubt in the coding part....
Suppose if there is some variable and if i want to use that variable as a constant in other part of my program....can i do that and how can i???

 

[Mark Curry]

In article <1a68a3b6-fa3a-47ff-b6b1-05da3dde0e5d@googlegroups.com>,
<venu.chitta1992@gmail.com> wrote:

<snip>

Okay...i got you Mark...thank you but i had another doubt in the coding
part....Suppose if there is some variable and if i want to use that
variable as a constant in other part of my program....can i do that and
how can i???

Forget "variable", "constant", and "program". That's software.
Think "reg", "wire", and "design". This is hardware.

Declare a wire (of appropriate width). Assign it to a value. Could be
a constant, could be a function of some other wires, and/or regs. Use
that wire anywhere you please.

Or declare it as a register (of appropriate width), and assign it within
a procedure (always block). Use it wherever you please. Just don't assign
to it from more than one block.

In either case, if you need it in another module, then make it a port
and connect it to the other module.

Got a feeling you're asking something else, but your question isn't clear,
and I'm not sure how it's related to the rest of the thread...

--Mark