Regarding BIST in FPGA

[Varun Jindal]

Hello ,

I am an engineering student and am working on testability issues in
FPGA devices. Can anybody throw light on the BIST schemes used by
Xilinx in their devices ; i.e. how do they achieve 100% fault
coverage;whether they use soft BIST or hard BIST. Any information will
be appreciated. Thanks in advance.

Regds.
Varun

 

[Austin Lesea]

Varun,

Search the USPTO for our patents on BIST in PLD.

Austin

Varun Jindal wrote:

Hello ,

I am an engineering student and am working on testability issues in
FPGA devices. Can anybody throw light on the BIST schemes used by
Xilinx in their devices ; i.e. how do they achieve 100% fault
coverage;whether they use soft BIST or hard BIST. Any information will
be appreciated. Thanks in advance.

Regds.
Varun

 

[Peter Alfke]

go to google.com and enter: BIST Xilinx
and you will find over 2000 hits. Have fun!
Peter Alfke

From: Austin Lesea <austin@xilinx.com
Organization: Xilinx,Inc
Newsgroups: comp.arch.fpga
Date: Wed, 18 Aug 2004 09:38:05 -0700
Subject: Re: Regarding BIST in FPGA

Varun,

Search the USPTO for our patents on BIST in PLD.

Austin

Varun Jindal wrote:
Hello ,

I am an engineering student and am working on testability issues in
FPGA devices. Can anybody throw light on the BIST schemes used by
Xilinx in their devices ; i.e. how do they achieve 100% fault
coverage;whether they use soft BIST or hard BIST. Any information will
be appreciated. Thanks in advance.

Regds.
Varun