reg, wire usage question

B

bbrady

Guest
Hi everyone,

I'm a little confused about an issue with regs and wires. I know what
both are used for and the differences between the two. However, I just
stumbled across a detail in the verilog standard that confused me. If
you declare something as a reg, apparently, you aren't allowed to also
declare it as a wire. In Section 4.2.2 Variable Declarations, it
states that it is illegal to redeclare a name already declared by a
net, ...

I've seen many times a name declared as a wire and a reg. Until a
moment ago, I actually thought this was what you were supposed to do.
Was this the case in an older version of Verilog, or have I just seen
many examples of incorrectly written Verilog code?

Now, this brings me to another (more important) question. I'm working
on a tool that will automatically translate Verilog to a formal
language. In one of the designs I'm working with, there are many
signals declared as both wires and regs. What should I do? Correct the
Verilog so that signals aren't defined as both wires and regs? Or is
there some other way to deal with this?

Thanks,
bryan
 
On Thu, 19 Jul 2007 21:22:35 -0000,
bbrady <bryan.brady@gmail.com> wrote:

I've seen many times a name declared as a wire and a reg. Until a
moment ago, I actually thought this was what you were supposed to do.
Was this the case in an older version of Verilog, or have I just seen
many examples of incorrectly written Verilog code?
Click to expand...
As you said in your post, it's definitely illegal to have a wire and
a reg with the same name in the same scope; and this has been true
for (as far as I know) the whole life of Verilog.

I wonder if you're thinking of this syntax:

module (A, Y);
input A; // A is a wire
output Y; // Y *would* be a wire...
reg Y; // but we redeclare it as a reg

Or (much less likely) this SystemVerilog syntax, which is
not yet supported by most simulators:

wire logic a;

Now, this brings me to another (more important) question. I'm working
on a tool that will automatically translate Verilog to a formal
language. In one of the designs I'm working with, there are many
signals declared as both wires and regs. What should I do?
Click to expand...
Panic. Such code is irredeemably broken.

Are you *sure* you have conflicting declarations? Can you show
us a sample of this situation?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
As you said in your post, it's definitely illegal to have a wire and
a reg with the same name in the same scope; and this has been true
for (as far as I know) the whole life of Verilog.

I wonder if you're thinking of this syntax:

module (A, Y);
input A; // A is a wire
output Y; // Y *would* be a wire...
reg Y; // but we redeclare it as a reg
Click to expand...
No, but I think this helped confuse me. You can also say:
output reg Y; which does the same thing. Until today, I thought reg
was just a "modifier" (sort of like unsigned in C/C++, for instance).

Are you *sure* you have conflicting declarations? Can you show
us a sample of this situation?
Click to expand...
In the example below, I've removed everything except the basic
structure of the file, which should be sufficient.

module somemod(some ports);

.... skip a bunch of stuff ...

wire [31:0] v0M_rdata;
reg [31:0] v0M_rdata, v0M_nxt_rdatal;

always @(*) /* combinational block*/
begin
...
v0M_nxt_rdata1 = some_expression;
...
end

always @(posedge clk)
begin
...
v0M_nxt_rdata <= whatever;
...
end

endmodule
 
I made a mistake in my example in the previous post. The following
example is what I meant.

module somemod(some ports);

... skip a bunch of stuff ...

wire [31:0] v0M_rdata;
reg [31:0] v0M_rdata, v0M_nxt_rdatal;

always @(*) /* combinational block*/
begin
...
v0M_nxt_rdata1 = some_expression;
...
end

always @(posedge clk)
begin
...
v0M_rdata <= v0M_nxt_rdata1;
...
end

endmodule
Click to expand...
 
This is not possible
Now now you tell me, how do refer to a signal then
the register and the wires have different semantics all together,

It is like signals and variables in VHDL

Which one are you expecting when you say somemod.v0M_rdata

IN Verilogs lifetime, it did not have this. Moreover, Verilog
compilers are finally software and not rocket scientists that can feel
the pulse of a statement and remove ambiguity by assumption
-Parag
 
On Fri, 20 Jul 2007 04:19:49 -0000, bbrady <bryan.brady@gmail.com>
wrote:

The following
example is what I meant.

module somemod(some ports);

... skip a bunch of stuff ...

wire [31:0] v0M_rdata;
reg [31:0] v0M_rdata, v0M_nxt_rdatal;
Click to expand...
Which tool compiles this without error?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Jul 20, 4:43 am, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
wrote:
This is not possible
Now now you tell me, how do refer to a signal then
the register and the wires have different semantics all together,

It is like signals and variables in VHDL

Which one are you expecting when you say somemod.v0M_rdata

IN Verilogs lifetime, it did not have this. Moreover, Verilog
compilers are finally software and not rocket scientists that can feel
the pulse of a statement and remove ambiguity by assumption
-Parag
Click to expand...

Can rocket scientists do that? My opinion of them has definitely gone
up two notches :)

I, too would like to know what synthesizer or simulator doesn't mark
this code as an error. In my recollection I would get errors like
"v0M_rdata has already been defined in this context". In fact this
usually happens to me when I declare a reg after using it in a module
port list, where the compiler has automatically made it a wire. Is
it possible that the compiler in this case ignores the first
definition
because the wire had no references until after the reg definition?

confused,
Gabor
 
On Jul 20, 9:40 am, gabor <ga...@alacron.com> wrote:
On Jul 20, 4:43 am, "parag_p...@hotmail.com" <parag_p...@hotmail.com
wrote:

This is not possible
Now now you tell me, how do refer to a signal then
the register and the wires have different semantics all together,

It is like signals and variables in VHDL

Which one are you expecting when you say somemod.v0M_rdata

IN Verilogs lifetime, it did not have this. Moreover, Verilog
compilers are finally software and not rocket scientists that can feel
the pulse of a statement and remove ambiguity by assumption
-Parag

Can rocket scientists do that? My opinion of them has definitely gone
up two notches :)

I, too would like to know what synthesizer or simulator doesn't mark
this code as an error. In my recollection I would get errors like
"v0M_rdata has already been defined in this context". In fact this
usually happens to me when I declare a reg after using it in a module
port list, where the compiler has automatically made it a wire. Is
it possible that the compiler in this case ignores the first
definition
because the wire had no references until after the reg definition?

confused,
Gabor
Click to expand...

O.K. I had to try it myself:


wire [7:0] foo;
reg [7:0] foo;

always @* foo = something;

Synplify:
@E: CG341 :"C:\projects\fastx\hexcl\dualcl_async_ddr.v":129:10:129:12|
foo is already declared in this scope.
XST:
ERROR:HDLCompilers:27 - ../source/FastVideo1.v line 272 Illegal
redeclaration of 'foo'
ModelSim:
# ** Error: test_top.v(82): foo already declared in this scope
(test_top)

That's all the Verilog compilers I have - all agree it's an error.
 
It should be a plain check in Yacc or a GA stage after that in
compialtion . Semantic check wll catch this


VCS will compile but will give you a notice

Parsing design file 'p1.v'
Warning-[IPDW] Identifier previously declared
Second declaration for identifier 'a' ignored
"p1.v", 3
Top Level Modules:


I think, Brady was using a VCS and did not see the compile time
messages at all
 
gabor <gabor@alacron.com> wrote:
....

O.K. I had to try it myself:
Click to expand...

foo;
reg [7:0] foo;

always @* foo = something;

Synplify:
@E: CG341 :"C:\projects\fastx\hexcl\dualcl_async_ddr.v":129:10:129:12|
foo is already declared in this scope.
XST:
ERROR:HDLCompilers:27 - ../source/FastVideo1.v line 272 Illegal
redeclaration of 'foo'
ModelSim:
# ** Error: test_top.v(82): foo already declared in this scope
(test_top)

iverilog test.v
test.v:4: foo definition conflicts with definition at test.v:3.
Click to expand...
XXXX type=reg, curtype=wire
cver test.v
GPLCVER_2.11a of 07/05/05 (Linux-elf).
Click to expand...
Copyright (c) 1991-2005 Pragmatic C Software Corp.
All Rights reserved. Licensed under the GNU General Public License (GPL).
See the 'COPYING' file for details. NO WARRANTY provided.
Today is Fri Jul 20 21:43:15 2007.
Compiling source file "test.v"
**test.v(4) ERROR** [1014] reg foo previously declared as wire at **test.v(3)
Unable to begin simulation.
There were 1 error(s), 0 warning(s), and 0 inform(s).
End of GPLCVER_2.11a at Fri Jul 20 21:43:15 2007 (elapsed 0.1 seconds).

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
I didn't compile it with anything. I'm writing a tool to translate
Verilog into a formal language. Its been years since I've actually
designed anything in Verilog.

Parag: Which one are you expecting when you say somemod.v0M_rdata
that was the source of my confusion, I thought reg was a modifier,
i.e., not a *separate* variable, so there is only one
somemod.v0M_rdata

Thanks everyone for your help. Thanks Parag for being sarcastic.
 
Sorry Brady
if you feel so .
Lately , even others are feeling a tone of sarcasm in my
communications.
( Rocket scientist and all was just a figment of imagination ) Excuse
them at your own ease


Sorry for the wide distribution, but if others feel so. I apologize.
I will restrain
 
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