reg to wire

[Anshul Bansal]

Hello All

I am trying to use the following specify block in my program.

reg nX1, nX0, X1, X0;

specify

specparam D1=10;
specparam D2=20;
(A0,A1,B0,B1,Xe,en *> nX1) = D1;
(A0,A1,B0,B1,Xe,en *> nX0) = D1;
(A0,A1,B0,B1,Xe,en *> X0) = D2;
(A0,A1,B0,B1,Xe,en *> X1) = D2;

endspecify

I am also using an "always" block further down in my program which uses
the values of nX1, nX0, X0 and X1.

When I try to compile this entire design in NC Verilog simulator then
it gives me an error that "Register Encountered in specify block".

So I figured out that I can't use registers in specify block. Moreover
when I compile the same design in Modelsim simulator, it
compiles properly without giving any error.

So I need to convert the reg to wire somehow before the specify block
and then convert wire back to reg after the specify block so that I can
use them in the always block. Can you give me directions and specific
commands (if any) to do this.

Please help.

Thanks

Anshul

 

[Neo]

But I dont understand why that should be a problem for the tool as
specify block is just used for pin to pin delays and has nothing to do
with they being registers of wires.

 

[MysticSage]

Actually it is same behavior with VCS. I do not know what should be
standard behavior. Fix can be declaring tmp wire as shown below

reg nX1, nX0, X1, X0;

wire nX1tmp, nX0tmp, X1tmp, X0tmp;

specify

specparam D1=10;
specparam D2=20;
(A0,A1,B0,B1,Xe,en *> nX1tmp) = D1;
(A0,A1,B0,B1,Xe,en *> nX0tmp) = D1;
(A0,A1,B0,B1,Xe,en *> X0tmp) = D2;
(A0,A1,B0,B1,Xe,en *> X1tmp) = D2;

endspecify

always @(nX1tmp) nX1 = nX1tmp;
.....
.....

 

Neo wrote:

But I dont understand why that should be a problem for the tool as
specify block is just used for pin to pin delays and has nothing to
do
with they being registers of wires.

The concept of delays has a lot to do with being wires versus
registers.

Verilog has the concept of a delay on a wire. You can declare a wire
to have a delay, and that delay will occur between any driver of the
wire and the readers of the wire. This is essentially implemented by
inserting a delay element, much like a gate primitive, which drives the
delayed wire.

However, a reg works like an ordinary programming language variable.
If you write to it, its value changes instantly. You can write to it
and read it in the next statement and see the new value. If it didn't
work that way, it would be very hard to write procedural code. Even a
delayed nonblocking assignment is not a delay on the reg; instead it
creates a process that waits appropriately, and then updates the reg
with an instantaneous write. This can be seen in the behavior when
nonblocking assignments are interleaved with blocking ones. A reg also
can't be driven by a primitive. The conceptual model used for
inserting delays on wires isn't directly applicable to regs.

As you say, a path delay is a pin to pin delay for the module. But for
an output port declared as a reg, the reg is not actually the pin. The
pin is the wire that comes out of the module port. The reg is a local
thing that does not leave the module. There is an implicit continuous
assignment from the reg to a wire that actually leaves the module and
is the pin (i.e. the output port as seen from the outside). Being able
to declare an output port as a reg is just a shorthand to save you from
having to declare a separate local reg and a continuous assignment from
the reg to the output port wire.

It would be possible to implement the pin to pin delay by putting the
delay element on the actual output port: the net that comes out of the
module. This would make the most sense. However, this means that the
delayed value would not be visible inside the module. Inside the
module, the port name refers to the local reg, not the delayed net.
The local reg would continue to behave like a variable should, with
writes immediately affecting its value. This could be surprising to
anyone expecting to see the effect of the delay on the supposed "port".

Note that it is possible to get this behavior for yourself, by
explicitly declaring a local reg and a continuous assignment from the
reg to an output port wire. Then the path delay can be applied to the
output port wire. In this situation, you would have access to both the
reg and to the delayed wire.