reg is shown in waveform window of QuestaSim6.2b

[gck]

I wrote following program,

module pipe ( out, in, clk );
output out; reg out;
input in, clk;

always @(in)
@(posedge clk)
out <= repeat(2) @(posedge clk) in;

endmodule

I am using QuestSim 6.2b
When I compile using vlog and simulate using vsim.
I have tried to add the signals to waveform using add waves *.
I have found that only signal "in" and "clk" is visible and "out" is
not visible.
It not been shown in signal window also.

I tried same program on Modelsim 6.3c some other PC, its working fine
overthere.

Please Help me.

Thanks in advance

 

[Andreas Ehliar]

On 2008-10-21, gck <gkhedkar@gmail.com> wrote:

When I compile using vlog and simulate using vsim.
I have tried to add the signals to waveform using add waves *.
I have found that only signal "in" and "clk" is visible and "out" is
not visible.
It not been shown in signal window also.

Is this a part of a larger design? In that case I would guess that
the optimizer have transformed this signal in such a way that it is not
possible to show it any longer.

If you compile the design with the +acc flag given to vlog you should be
able to see the signal again.

/Andreas

 

[HT-Lab]

"gck" <gkhedkar@gmail.com> wrote in message
news:9e29c589-2d3a-4399-9a0d-56296215bd62@z6g2000pre.googlegroups.com...

I wrote following program,

module pipe ( out, in, clk );
output out; reg out;
input in, clk;

always @(in)
@(posedge clk)
out <= repeat(2) @(posedge clk) in;

endmodule

I am using QuestSim 6.2b
When I compile using vlog and simulate using vsim.
I have tried to add the signals to waveform using add waves *.
I have found that only signal "in" and "clk" is visible and "out" is
not visible.
It not been shown in signal window also.

I tried same program on Modelsim 6.3c some other PC, its working fine
overthere.

Please Help me.

Thanks in advance

What about updating your Questa to 6.3c or the latest 6.4a?

Hans
www.ht-lab.com