Reg DCM_CLKGEN primitive for Spartan-6

[Aditi]

Hi all,


I am working on a Spartan-6 FPGA.


I am using a DCM (DCM_CLKGEN Primitive) to generate some clock rates
that I want to.

Here is how I declare the DCM


DCM_CLKGEN g723clk_dcm (

.CLKIN ( fpgaclk ),
.RST ( dcm_rst_g723 ),
.LOCKED (lock_val_g723),
.CLKFX ( codec_286m_dcm ),
.CLKFX180 ( codec_286m_180p)

);

defparam g723clk_dcm.CLKIN_PERIOD = 50;
defparam g723clk_dcm.CLKFX_MULTIPLY = 143;
defparam g723clk_dcm.CLKFX_DIVIDE = 10;

// synthesis attribute CLKIN_PERIOD of g723clk_dcm is 50;
// synthesis attribute CLKFX_MULTIPLY of g723clk_dcm is 143;
// synthesis attribute CLKFX_DIVIDE of g723clk_dcm is 10;


I am getting a warning like this


"The DCM, g723clk_dcm, has the attribute
DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase
relationship exists
between the input clock and CLKFX or CLKFX180 outputs of this DCM.
Data paths
between these clock domains must be constrained using FROM/TO
constraints."


Can somebody let me know what could be the reason for this warning?

Am I doing any wrong in declaring the DCM?


Thanks,

Regards,

Aditi.

 

[Gabor]

On Thursday, March 17, 2011 8:38:16 PM UTC-4, Aditi wrote:

Hi all,


I am working on a Spartan-6 FPGA.


I am using a DCM (DCM_CLKGEN Primitive) to generate some clock rates
that I want to.

Here is how I declare the DCM


DCM_CLKGEN g723clk_dcm (

.CLKIN ( fpgaclk ),
.RST ( dcm_rst_g723 ),
.LOCKED (lock_val_g723),
.CLKFX ( codec_286m_dcm ),
.CLKFX180 ( codec_286m_180p)

);

defparam g723clk_dcm.CLKIN_PERIOD = 50;
defparam g723clk_dcm.CLKFX_MULTIPLY = 143;
defparam g723clk_dcm.CLKFX_DIVIDE = 10;

// synthesis attribute CLKIN_PERIOD of g723clk_dcm is 50;
// synthesis attribute CLKFX_MULTIPLY of g723clk_dcm is 143;
// synthesis attribute CLKFX_DIVIDE of g723clk_dcm is 10;


I am getting a warning like this


"The DCM, g723clk_dcm, has the attribute
DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase
relationship exists
between the input clock and CLKFX or CLKFX180 outputs of this DCM.
Data paths
between these clock domains must be constrained using FROM/TO
constraints."


Can somebody let me know what could be the reason for this warning?

Am I doing any wrong in declaring the DCM?


Thanks,

Regards,

Aditi.

In your case you can probably ignore the warning. The output
clock should be considered asynchronous to the input clock.
Given the fact that you asked for a frequency generator,
this does not seem worthy of a warning. If however you
want the output clock to line up with the input clock
exactly every 143 cycles, then you should do something
about the warning. If you're new to Xilinx FPGA's
and their Core Generator and other IP offerings,
you should get used to seeing warnings. Xilinx's
approach is to warn about anything remotely interesting
and then offer you a report viewer with a filter.

-- Gabor