reg assignment inside task

For simulation, I'm used to initializing regs as I declare them in a
module:

reg [7:0] cnt = 0;
reg reset = 1;

Is it legal to do a similar shortcut in a task?

task foo;
input [31:0] data;
output [31:0] o_data;

reg mode = 0;

begin
....
end
endtask

Thanks!

John P

 

jprovide...@yahoo.com wrote:

Is it legal to do a similar shortcut in a task?

task foo;
input [31:0] data;
output [31:0] o_data;

reg mode = 0;

Not in Verilog. It was disallowed because the behavior would not
match what users would probably expect. Since this is a static
variable, it would be initialized once at the start of simulation.
But users would probably expect it to be initialized each time the
task was called.

In SystemVerilog, it is allowed. For an automatic variable, it will
be initialized each time a new version of the variable is allocated,
which is each time the task is called.

For a static variable, it will be initialized once at the start of
simulation. To help avoid mistakes due to this, a requirement was
made in the Accellera SV LRM that a static variable with an
initializer had to be declared with an explicit "static" qualifier.
This requirement was improperly removed from the IEEE 2005 LRM, but is
expected to be reinstated in the next revision.