M
mcholbi
Guest
We are trying to implement a toplevel module which has an IN and an OU
port which are records. The synthesis works fine but we have the proble
that synplify converts these record ports in a big port lik
"i_inputs[80:0]" instead of single ports like i_inputs.in0, i_inputs_flag
i_inputs.enable ...
This way its impossible later to assign the pins of the FPGA in Designer t
the correct port. Is there anyway or work around to solve this problem o
to change this behaviour?
Can the pins be assigned before synthesis? in the sdc file? And if it i
possible which format do I use for the records?
Thanks and congratulations for the forum, always source of solutions!
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Posted through http://www.FPGARelated.com
port which are records. The synthesis works fine but we have the proble
that synplify converts these record ports in a big port lik
"i_inputs[80:0]" instead of single ports like i_inputs.in0, i_inputs_flag
i_inputs.enable ...
This way its impossible later to assign the pins of the FPGA in Designer t
the correct port. Is there anyway or work around to solve this problem o
to change this behaviour?
Can the pins be assigned before synthesis? in the sdc file? And if it i
possible which format do I use for the records?
Thanks and congratulations for the forum, always source of solutions!
---------------------------------------
Posted through http://www.FPGARelated.com