record and array synthesis

[BlueDoze]

Hello,

I'd like to know how the VHDL record type and array type is
synthesized, assuming all the field are synthesizable ?

Bluedoze

 

[Mike Treseler]

BlueDoze wrote:

I'd like to know how the VHDL record type and array type is
synthesized, assuming all the field are synthesizable ?

It depends on your code.
A record or array type could represent rom or ram,
a set of registers, or an intermediate value.
The job of synthesis
is to provide a netlist that sims the
same as the source code.

Consider keeping entities simple
and use the complex types in processes
or architectures.

-- Mike Treseler

 

[Wallclimber]

I'd like to know how the VHDL record type and array type is
synthesized, assuming all the field are synthesizable ?

Generally yes. In our designs, we are using records, array's, records
with arrays and arrays with records pretty much everywhere in our
code, including port definitions.

At least Synopsys DC, SynAsic and Synplify have no problems with it.
Just make sure that the toplevel block of the design has std_(u)logic
otherwise it may be difficult to track signals during Place & Route.

That said, if you're working in a company, it doesn't hurt to check if
there are rules in your department that forbid the use of these
constructs.

Tom Verbeure