Real values in sub block

[Kenneth Brun Nielsen]

How can I parse analogue (real) values from one hierarchial module to
another (its parent)? Can I have inputs/outputs of a "real/float"
type, or do have have to convert them into a digital word?

Best regards,
Kenneth

 

[Jonathan Bromley]

On Wed, 1 Jul 2009 05:52:51 -0700 (PDT), Kenneth Brun Nielsen wrote:

How can I parse

pass?

analogue (real) values from one hierarchial module to
another (its parent)? Can I have inputs/outputs of a "real/float"
type, or do have have to convert them into a digital word?

Verilog doesn't allow "real" ports, because ports must be
nets on at least one side of the port boundary and you
can't have "real" nets. SystemVerilog *does* allow it,
because you can have a port wth variables on both sides.

Verilog does have a straightforward way to fix this.
There are two conversion functions, $realtobits and
$bitstoreal, that convert real values to/from 64-bit
vector values (actually the IEEE-754 representation).
The 64-bit values can then be shipped across a port
in the usual way.

If you're trying to model real-world analog behaviour,
it may be better to use the trick I have previously
shown here for conveying an arbitrary bit-string
over a one-bit wire, using a zero-time 3-level
coding technique.

Nothing, but NOTHING, to do with reals in Verilog
will be synthesizable.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Thu, 2 Jul 2009 01:30:38 -0700 (PDT), Kenneth Brun Nielsen wrote:

If you're trying to model real-world analog behaviour,
it may be better to use the trick I have previously
shown here for conveying an arbitrary bit-string
over a one-bit wire, using a zero-time 3-level
coding technique.

I tried searching, but without results. Can you please provide a link?

http://groups.google.com/group/comp.lang.verilog/msg/fbb57b2fc1d78207

The code is OK, but there are a couple of errors in the comments;
see later messages in the same thread.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kenneth Brun Nielsen]

On 1 Jul., 16:10, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

Verilog doesn't allow "real" ports, because ports must be
nets on at least one side of the port boundary and you
can't have "real" nets.  SystemVerilog *does* allow it,
because you can have a port wth variables on both sides.

Verilog does have a straightforward way to fix this.
There are two conversion functions, $realtobits and
$bitstoreal, that convert real values to/from 64-bit
vector values (actually the IEEE-754 representation).
The 64-bit values can then be shipped across a port
in the usual way.

OK. Thanks.

If you're trying to model real-world analog behaviour,
it may be better to use the trick I have previously
shown here for conveying an arbitrary bit-string
over a one-bit wire, using a zero-time 3-level
coding technique.

It's not really analogue modelling. It is read-out of some analog
voltage levels to be used IRL hardware testing. The values are read
from a LUT dependent on control bits within a (sub) module. Obviously,
I would like to access these "analogue" values from the (top level)
testbench.

Your coding technique sounds interesting, but I am new in this group.
I tried searching, but without results. Can you please provide a link?

Nothing, but NOTHING, to do with reals in Verilog
will be synthesizable.

No problem. I'm not synthesizing anything.

/Kenneth

 

[Jonathan Bromley]

On Fri, 3 Jul 2009 03:11:45 -0700 (PDT), Kenneth Brun Nielsen
<kenneth.brun.nielsen@googlemail.com> wrote:

Can I somehow access variables (registers) in another (child) module,
when the registers are NOT connected to a port.

Of course - just make a hierarchical reference. Verilog!=VHDL.

module device(...);
reg [7:0] a;
...
// other code that does stuff
...
endmodule

module testbench;
...
device child(...);
...

initial
// force child's 'a' to zero at start
child.a = 0;

always #10
// sample child's 'a' every 10 time units
$display("at time %0d signal = %b", $time, child.a);

// detect every transition on child's 'a'
always @(child.a) begin ... end

endmodule

Hierarchical references can be as deep as you like:
child.inner_instance.leaf_instance.sig

They can also be upwards, relative and absolute -
but we'll talk about that another day. Got to
leave you with _some_ incentive to buy a training
class
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kenneth Brun Nielsen]

On 2 Jul., 11:27, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

http://groups.google.com/group/comp.lang.verilog/msg/fbb57b2fc1d78207

The code is OK, but there are a couple of errors in the comments;
see later messages in the same thread.

Thanks. Did not implement it so far - but I got the idea.

Related to this subject I have another question:
Can I somehow access variables (registers) in another (child) module,
when the registers are NOT connected to a port. The case is, that I am
- to some extent - bounded by a design system, from where I extract
the Verilog netlist. Hence, it is not really desirable to add ports in
order to pass the analogue values from one block to another. If I do
it this way, I will have to add the code manually every time I re-
extract the netlist (due to changes or whatever).

The design system (Cadence) will complain if I create a (Verilog) port
in the module, if the same port is not present in the schematic
representation of the device.

Best regards,
Kenneth

 

[Jonathan Bromley]

On Fri, 3 Jul 2009 04:47:05 -0700 (PDT), Kenneth Brun Nielsen wrote:

Well, I got a Verilog book four inches wide But it stinks as a
reference, and spends most of its pages showing truth tables for a
range of more or less simple circuits. It seems I bought the wrong
book.

With apologies for the advertisement, this may press
the right buttons for you. Not too many truth tables,
plenty of tips and gotchas:

http://www.doulos.com/content/products/golden_reference_guides.php

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Kenneth Brun Nielsen]

On 3 Jul., 12:23, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

Of course - just make a hierarchical reference.  Verilog!=VHDL.

Perfect! Just what I needed.

Hierarchical references can be as deep as you like:
  child.inner_instance.leaf_instance.sig

Nice and simple

They can also be upwards, relative and absolute -
but we'll talk about that another day.  Got to
leave you with _some_ incentive to buy a training
class

Hehe.

Well, I got a Verilog book four inches wide But it stinks as a
reference, and spends most of its pages showing truth tables for a
range of more or less simple circuits. It seems I bought the wrong
book. I learned VHDL years ago (practically never used it since,
though), so I understand the basics of modelling languages. But, as
you state, there are various differences between the languages (not
related to syntax only). The perfect book in my situation would sketch
the cold details of the language, include a list of keywords, data
types and functions. And NOT including basic knowledge about adders,
multipliers, RISC processor etc.

All this just to say, that training classes are probably overkill in
my situation. The assignment is close to a once-in-a-lifetime, and it
is not very complex (simple digital modelling for an mixed-signal
design of mine) - even for my limited skills. It would be nice to
understand more aspects of Verilog. NICE, but - at the time being -
not NEEDed

Enough stories told. Thank you very much for your help on this

Best regards,
Kenneth