K
kb33
Guest
Hi,
I have always used the following methodology for testing my verilog
modules:
1. Prepare a test bench that instantiates within itself the Design
under test (DUT);
2. Provide the stimuli (clock, reset, other inputs) to the DUT within
the testbench;
3. End the simulation with a $finish statement when all the required
amount of stimulus/ testing has been accomplished.
The test bench is compiled and simulated in one go. However, if I need
to test my DUT using live signals (not on the actual hardware, but
using the test bench environment), how can I do so? Do any of the
verilog simulators provide such a feature?
Thanks,
Kanchan
I have always used the following methodology for testing my verilog
modules:
1. Prepare a test bench that instantiates within itself the Design
under test (DUT);
2. Provide the stimuli (clock, reset, other inputs) to the DUT within
the testbench;
3. End the simulation with a $finish statement when all the required
amount of stimulus/ testing has been accomplished.
The test bench is compiled and simulated in one go. However, if I need
to test my DUT using live signals (not on the actual hardware, but
using the test bench environment), how can I do so? Do any of the
verilog simulators provide such a feature?
Thanks,
Kanchan