Real port types in VHDL

Hello all,

Which VHDL simulator with waveform analyzer supports real type ports?
Both ModelSim and NCSIM allow real type computations but are shy of
the real type ports.

Yaseen

 

[Alan Fitch]

yaseenzaidi@netzero.com wrote:

Hello all,

Which VHDL simulator with waveform analyzer supports real type ports?
Both ModelSim and NCSIM allow real type computations but are shy of
the real type ports.

Yaseen

There should be no problem. In fact I just tried it in modelsim and it
worked.

The only issue is the initial value of real which is the maximum
negative real number. If you then do something such as multiply two
inputs, you exceed the valid range and get a run time error.

Here's my code which works,

Alan

entity e is
port (i1,i2 : in real;
o : out real);
end entity e;

architecture a of e is

begin
o <= i1 * i2;
end architecture a;


entity etb is
end entity etb;

architecture bench of etb is

signal i1, i2, o : real := 0.0; -- this is important to avoid overflow

begin

u1 : entity work.e
port map (i1 => i1,
i2 => i2,
o => o);

process
begin
i1 <= 0.0;
i2 <= 0.0;
wait for 10 ns;
i1 <= 1.1;
i2 <= 2.2;
wait for 10 ns;
wait;
end process;
end architecture bench;


--
Alan Fitch

 

[Mike Treseler]

Alan Fitch wrote:

Here's my code which works,

It does, but why the break with local traditions?

I inserted a few of these: report (real'image(o));
and I can see it in text:

# vsim -c etb
# Loading work.etb(bench)
# Loading work.real_port(synth)
VSIM 1> run
# ** Note: -1.000000e+308
# Time: 0 ns Iteration: 0 Instance: /etb
# ** Note: 0.000000e+00
# Time: 10 ns Iteration: 0 Instance: /etb
# ** Note: 2.420000e+00
# Time: 20 ns Iteration: 0 Instance: /etb
VSIM 2>

Thanks for the posting.

-- Mike Treseler

 

[Jonathan Bromley]

On Thu, 14 Aug 2008 11:14:06 -0700, Mike Treseler
<mtreseler@gmail.com> wrote:

Alan Fitch wrote:

Here's my code which works,

It does, but why the break with local traditions?

In defence of my colleague Alan, I should point out that
the local tradition chez nous is, as far as possible, to
write code that works. Human frailty and the general
cussedness of engineering artefacts being what they are,
that goal is not always achieved - but we try

It might be worth adding a caveat to this debate. If
you use signals of real type, which you are quite
entitled to do, you should be careful NOT to use
events on such signals to trigger other activity.
The VHDL LRM explicitly says that any model that
depends on detection of events on a real signal
is "non-portable" - in other words, what works on
one simulator might not work on another. So: no
real signals in a sensitivity list, please, and
no "wait until" or "wait on" real signals.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Alan Fitch]

Jonathan Bromley wrote:

On Thu, 14 Aug 2008 11:14:06 -0700, Mike Treseler
mtreseler@gmail.com> wrote:

Alan Fitch wrote:

Here's my code which works,
It does, but why the break with local traditions?

Actually I wasn't aware of the local tradition :-(
I've only just started posting here again recently...
Luckily Jonathan has come to my defence!

In defence of my colleague Alan, I should point out that
the local tradition chez nous is, as far as possible, to
write code that works. Human frailty and the general
cussedness of engineering artefacts being what they are,
that goal is not always achieved - but we try

It might be worth adding a caveat to this debate. If
you use signals of real type, which you are quite
entitled to do, you should be careful NOT to use
events on such signals to trigger other activity.
The VHDL LRM explicitly says that any model that
depends on detection of events on a real signal
is "non-portable" - in other words, what works on
one simulator might not work on another. So: no
real signals in a sensitivity list, please, and
no "wait until" or "wait on" real signals.

I did wonder if this is affected by mandating IEEE p754?
In VHDL 87 and 93, floating point was vendor defined. In 2002,
it is specified as being P754 or P854. Does that mean that detecting an
event on a real signal is portable across simulators? I don't know if
complying to IEEE floating point implies identical (bit true) results on
all machines?

I've just looked at VHDL 2002 and it says

"An implementation must choose a representation for all floating-point
types except for universal_real that
conforms either to IEEE Std 754 or to IEEE Std 854; in either case, a
minimum representation size of 64 bits
is required for this chosen representation."

so I guess that it's still unsafe to detect events on real,


Alan


--
Alan Fitch